se.py revision 8887
18706Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 135369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 143005Sstever@eecs.umich.edu# All rights reserved. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253005Sstever@eecs.umich.edu# this software without specific prior written permission. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383005Sstever@eecs.umich.edu# 393005Sstever@eecs.umich.edu# Authors: Steve Reinhardt 403005Sstever@eecs.umich.edu 412710SN/A# Simple test script 422710SN/A# 433005Sstever@eecs.umich.edu# "m5 test.py" 442889SN/A 456654Snate@binkert.orgimport os 466654Snate@binkert.orgimport optparse 476654Snate@binkert.orgimport sys 486654Snate@binkert.orgfrom os.path import join as joinpath 496654Snate@binkert.org 502667SN/Aimport m5 516654Snate@binkert.orgfrom m5.defines import buildEnv 526654Snate@binkert.orgfrom m5.objects import * 536654Snate@binkert.orgfrom m5.util import addToPath, fatal 545457Ssaidi@eecs.umich.edu 556654Snate@binkert.orgaddToPath('../common') 568169SLisa.Hsu@amd.comaddToPath('../ruby') 578169SLisa.Hsu@amd.com 588169SLisa.Hsu@amd.comimport Ruby 596654Snate@binkert.org 603395Shsul@eecs.umich.eduimport Simulation 616981SLisa.Hsu@amd.comimport CacheConfig 623448Shsul@eecs.umich.edufrom Caches import * 635369Ssaidi@eecs.umich.edufrom cpu2000 import * 643394Shsul@eecs.umich.edu 653444Sktlim@umich.edu# Get paths we might need. It's expected this file is in m5/configs/example. 663444Sktlim@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 673444Sktlim@umich.educonfig_root = os.path.dirname(config_path) 683444Sktlim@umich.edum5_root = os.path.dirname(config_root) 692424SN/A 702957SN/Aparser = optparse.OptionParser() 712957SN/A 723323Shsul@eecs.umich.edu# Benchmark options 733005Sstever@eecs.umich.eduparser.add_option("-c", "--cmd", 747787SAli.Saidi@ARM.com default=joinpath(m5_root, "tests/test-progs/hello/bin/%s/linux/hello" % \ 757787SAli.Saidi@ARM.com buildEnv['TARGET_ISA']), 765514SMichael.Adler@intel.com help="The binary to run in syscall emulation mode.") 772957SN/Aparser.add_option("-o", "--options", default="", 785514SMichael.Adler@intel.com help='The options to pass to the binary, use " " around the entire string') 795514SMichael.Adler@intel.comparser.add_option("-i", "--input", default="", help="Read stdin from a file.") 805514SMichael.Adler@intel.comparser.add_option("--output", default="", help="Redirect stdout to a file.") 815514SMichael.Adler@intel.comparser.add_option("--errout", default="", help="Redirect stderr to a file.") 828467Snilay@cs.wisc.edu 833444Sktlim@umich.eduexecfile(os.path.join(config_root, "common", "Options.py")) 842957SN/A 858862Snilay@cs.wisc.eduif '--ruby' in sys.argv: 868862Snilay@cs.wisc.edu Ruby.define_options(parser) 878467Snilay@cs.wisc.edu 882957SN/A(options, args) = parser.parse_args() 892957SN/A 902957SN/Aif args: 912957SN/A print "Error: script doesn't take any positional arguments" 922957SN/A sys.exit(1) 932957SN/A 948167SLisa.Hsu@amd.commultiprocesses = [] 958167SLisa.Hsu@amd.comapps = [] 968167SLisa.Hsu@amd.com 975369Ssaidi@eecs.umich.eduif options.bench: 988167SLisa.Hsu@amd.com apps = options.bench.split("-") 998167SLisa.Hsu@amd.com if len(apps) != options.num_cpus: 1008167SLisa.Hsu@amd.com print "number of benchmarks not equal to set num_cpus!" 1018167SLisa.Hsu@amd.com sys.exit(1) 1028167SLisa.Hsu@amd.com 1038167SLisa.Hsu@amd.com for app in apps: 1048167SLisa.Hsu@amd.com try: 1058168SLisa.Hsu@amd.com if buildEnv['TARGET_ISA'] == 'alpha': 1068168SLisa.Hsu@amd.com exec("workload = %s('alpha', 'tru64', 'ref')" % app) 1078168SLisa.Hsu@amd.com else: 1088168SLisa.Hsu@amd.com exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app) 1098167SLisa.Hsu@amd.com multiprocesses.append(workload.makeLiveProcess()) 1108167SLisa.Hsu@amd.com except: 1118168SLisa.Hsu@amd.com print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app) 1125369Ssaidi@eecs.umich.edu sys.exit(1) 1135369Ssaidi@eecs.umich.eduelse: 1145369Ssaidi@eecs.umich.edu process = LiveProcess() 1155369Ssaidi@eecs.umich.edu process.executable = options.cmd 1165369Ssaidi@eecs.umich.edu process.cmd = [options.cmd] + options.options.split() 1178167SLisa.Hsu@amd.com multiprocesses.append(process) 1185369Ssaidi@eecs.umich.edu 1195369Ssaidi@eecs.umich.edu 1202801SN/Aif options.input != "": 1212801SN/A process.input = options.input 1225514SMichael.Adler@intel.comif options.output != "": 1235514SMichael.Adler@intel.com process.output = options.output 1245514SMichael.Adler@intel.comif options.errout != "": 1255514SMichael.Adler@intel.com process.errout = options.errout 1262418SN/A 1276391Sksewell@umich.edu 1286391Sksewell@umich.edu# By default, set workload to path of user-specified binary 1296391Sksewell@umich.eduworkloads = options.cmd 1306642Sksewell@umich.edunumThreads = 1 1316391Sksewell@umich.edu 1328649Snilay@cs.wisc.eduif options.cpu_type == "detailed" or options.cpu_type == "inorder": 1332833SN/A #check for SMT workload 1342833SN/A workloads = options.cmd.split(';') 1352833SN/A if len(workloads) > 1: 1362833SN/A process = [] 1372833SN/A smt_idx = 0 1382833SN/A inputs = [] 1395514SMichael.Adler@intel.com outputs = [] 1405514SMichael.Adler@intel.com errouts = [] 1412833SN/A 1422833SN/A if options.input != "": 1432833SN/A inputs = options.input.split(';') 1445514SMichael.Adler@intel.com if options.output != "": 1455514SMichael.Adler@intel.com outputs = options.output.split(';') 1465514SMichael.Adler@intel.com if options.errout != "": 1475514SMichael.Adler@intel.com errouts = options.errout.split(';') 1482833SN/A 1492833SN/A for wrkld in workloads: 1502833SN/A smt_process = LiveProcess() 1513005Sstever@eecs.umich.edu smt_process.executable = wrkld 1522833SN/A smt_process.cmd = wrkld + " " + options.options 1532833SN/A if inputs and inputs[smt_idx]: 1542833SN/A smt_process.input = inputs[smt_idx] 1555514SMichael.Adler@intel.com if outputs and outputs[smt_idx]: 1565514SMichael.Adler@intel.com smt_process.output = outputs[smt_idx] 1575514SMichael.Adler@intel.com if errouts and errouts[smt_idx]: 1585514SMichael.Adler@intel.com smt_process.errout = errouts[smt_idx] 1592833SN/A process += [smt_process, ] 1602833SN/A smt_idx += 1 1616642Sksewell@umich.edu numThreads = len(workloads) 1628718Snilay@cs.wisc.edu 1638169SLisa.Hsu@amd.comif options.ruby: 1648718Snilay@cs.wisc.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 1658718Snilay@cs.wisc.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 1668169SLisa.Hsu@amd.com sys.exit(1) 1678169SLisa.Hsu@amd.com 1688718Snilay@cs.wisc.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 1693395Shsul@eecs.umich.eduCPUClass.clock = '2GHz' 1706642Sksewell@umich.eduCPUClass.numThreads = numThreads; 1713005Sstever@eecs.umich.edu 1723395Shsul@eecs.umich.edunp = options.num_cpus 1733395Shsul@eecs.umich.edu 1743395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 1753323Shsul@eecs.umich.edu physmem = PhysicalMemory(range=AddrRange("512MB")), 1763395Shsul@eecs.umich.edu membus = Bus(), mem_mode = test_mem_mode) 1773395Shsul@eecs.umich.edu 1783395Shsul@eecs.umich.edufor i in xrange(np): 1798167SLisa.Hsu@amd.com system.cpu[i].workload = multiprocesses[i] 1803005Sstever@eecs.umich.edu 1818169SLisa.Hsu@amd.com if options.ruby: 1828845Sandreas.hansson@arm.com system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave 1838845Sandreas.hansson@arm.com system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave 1848169SLisa.Hsu@amd.com 1854968Sacolyte@umich.edu if options.fastmem: 1864968Sacolyte@umich.edu system.cpu[0].physmem_port = system.physmem.port 1874968Sacolyte@umich.edu 1888887Sgeoffrey.blake@arm.com if options.checker: 1898887Sgeoffrey.blake@arm.com system.cpu[i].addCheckerCpu() 1908887Sgeoffrey.blake@arm.com 1918887Sgeoffrey.blake@arm.comif options.ruby: 1928887Sgeoffrey.blake@arm.com options.use_map = True 1938887Sgeoffrey.blake@arm.com Ruby.create_system(options, system) 1948887Sgeoffrey.blake@arm.com assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 1958887Sgeoffrey.blake@arm.comelse: 1968887Sgeoffrey.blake@arm.com system.system_port = system.membus.slave 1978887Sgeoffrey.blake@arm.com system.physmem.port = system.membus.master 1988887Sgeoffrey.blake@arm.com CacheConfig.config_cache(options, system) 1998887Sgeoffrey.blake@arm.com 2008801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 2012902SN/A 2023481Shsul@eecs.umich.eduSimulation.run(options, root, system, FutureClass) 203