se.py revision 8706
18706Sandreas.hansson@arm.com# Copyright (c) 2012 ARM Limited
28706Sandreas.hansson@arm.com# All rights reserved.
38706Sandreas.hansson@arm.com#
48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall
58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual
68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating
78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software
88706Sandreas.hansson@arm.com# licensed hereunder.  You may use the software subject to the license
98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated
108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software,
118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form.
128706Sandreas.hansson@arm.com#
135369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan
143005Sstever@eecs.umich.edu# All rights reserved.
153005Sstever@eecs.umich.edu#
163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution;
233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its
243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
253005Sstever@eecs.umich.edu# this software without specific prior written permission.
263005Sstever@eecs.umich.edu#
273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
383005Sstever@eecs.umich.edu#
393005Sstever@eecs.umich.edu# Authors: Steve Reinhardt
403005Sstever@eecs.umich.edu
412710SN/A# Simple test script
422710SN/A#
433005Sstever@eecs.umich.edu# "m5 test.py"
442889SN/A
456654Snate@binkert.orgimport os
466654Snate@binkert.orgimport optparse
476654Snate@binkert.orgimport sys
486654Snate@binkert.orgfrom os.path import join as joinpath
496654Snate@binkert.org
502667SN/Aimport m5
516654Snate@binkert.orgfrom m5.defines import buildEnv
526654Snate@binkert.orgfrom m5.objects import *
536654Snate@binkert.orgfrom m5.util import addToPath, fatal
545457Ssaidi@eecs.umich.edu
556654Snate@binkert.orgif buildEnv['FULL_SYSTEM']:
566654Snate@binkert.org    fatal("This script requires syscall emulation mode (*_SE).")
575457Ssaidi@eecs.umich.edu
586654Snate@binkert.orgaddToPath('../common')
598169SLisa.Hsu@amd.comaddToPath('../ruby')
608169SLisa.Hsu@amd.com
618169SLisa.Hsu@amd.comimport Ruby
626654Snate@binkert.org
633395Shsul@eecs.umich.eduimport Simulation
646981SLisa.Hsu@amd.comimport CacheConfig
653448Shsul@eecs.umich.edufrom Caches import *
665369Ssaidi@eecs.umich.edufrom cpu2000 import *
673394Shsul@eecs.umich.edu
683444Sktlim@umich.edu# Get paths we might need.  It's expected this file is in m5/configs/example.
693444Sktlim@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__))
703444Sktlim@umich.educonfig_root = os.path.dirname(config_path)
713444Sktlim@umich.edum5_root = os.path.dirname(config_root)
722424SN/A
732957SN/Aparser = optparse.OptionParser()
742957SN/A
753323Shsul@eecs.umich.edu# Benchmark options
763005Sstever@eecs.umich.eduparser.add_option("-c", "--cmd",
777787SAli.Saidi@ARM.com    default=joinpath(m5_root, "tests/test-progs/hello/bin/%s/linux/hello" % \
787787SAli.Saidi@ARM.com            buildEnv['TARGET_ISA']),
795514SMichael.Adler@intel.com    help="The binary to run in syscall emulation mode.")
802957SN/Aparser.add_option("-o", "--options", default="",
815514SMichael.Adler@intel.com    help='The options to pass to the binary, use " " around the entire string')
825514SMichael.Adler@intel.comparser.add_option("-i", "--input", default="", help="Read stdin from a file.")
835514SMichael.Adler@intel.comparser.add_option("--output", default="", help="Redirect stdout to a file.")
845514SMichael.Adler@intel.comparser.add_option("--errout", default="", help="Redirect stderr to a file.")
858467Snilay@cs.wisc.edu
863444Sktlim@umich.eduexecfile(os.path.join(config_root, "common", "Options.py"))
872957SN/A
888482Snilay@cs.wisc.eduif buildEnv['PROTOCOL'] != 'None':
898482Snilay@cs.wisc.edu    parser.add_option("--ruby", action="store_true")
908482Snilay@cs.wisc.edu    if '--ruby' in sys.argv:
918482Snilay@cs.wisc.edu        Ruby.define_options(parser)
928467Snilay@cs.wisc.edu
932957SN/A(options, args) = parser.parse_args()
942957SN/A
952957SN/Aif args:
962957SN/A    print "Error: script doesn't take any positional arguments"
972957SN/A    sys.exit(1)
982957SN/A
998167SLisa.Hsu@amd.commultiprocesses = []
1008167SLisa.Hsu@amd.comapps = []
1018167SLisa.Hsu@amd.com
1025369Ssaidi@eecs.umich.eduif options.bench:
1038167SLisa.Hsu@amd.com    apps = options.bench.split("-")
1048167SLisa.Hsu@amd.com    if len(apps) != options.num_cpus:
1058167SLisa.Hsu@amd.com        print "number of benchmarks not equal to set num_cpus!"
1068167SLisa.Hsu@amd.com        sys.exit(1)
1078167SLisa.Hsu@amd.com
1088167SLisa.Hsu@amd.com    for app in apps:
1098167SLisa.Hsu@amd.com        try:
1108168SLisa.Hsu@amd.com            if buildEnv['TARGET_ISA'] == 'alpha':
1118168SLisa.Hsu@amd.com                exec("workload = %s('alpha', 'tru64', 'ref')" % app)
1128168SLisa.Hsu@amd.com            else:
1138168SLisa.Hsu@amd.com                exec("workload = %s(buildEnv['TARGET_ISA'], 'linux', 'ref')" % app)
1148167SLisa.Hsu@amd.com            multiprocesses.append(workload.makeLiveProcess())
1158167SLisa.Hsu@amd.com        except:
1168168SLisa.Hsu@amd.com            print >>sys.stderr, "Unable to find workload for %s: %s" % (buildEnv['TARGET_ISA'], app)
1175369Ssaidi@eecs.umich.edu            sys.exit(1)
1185369Ssaidi@eecs.umich.eduelse:
1195369Ssaidi@eecs.umich.edu    process = LiveProcess()
1205369Ssaidi@eecs.umich.edu    process.executable = options.cmd
1215369Ssaidi@eecs.umich.edu    process.cmd = [options.cmd] + options.options.split()
1228167SLisa.Hsu@amd.com    multiprocesses.append(process)
1235369Ssaidi@eecs.umich.edu
1245369Ssaidi@eecs.umich.edu
1252801SN/Aif options.input != "":
1262801SN/A    process.input = options.input
1275514SMichael.Adler@intel.comif options.output != "":
1285514SMichael.Adler@intel.com    process.output = options.output
1295514SMichael.Adler@intel.comif options.errout != "":
1305514SMichael.Adler@intel.com    process.errout = options.errout
1312418SN/A
1326391Sksewell@umich.edu
1336391Sksewell@umich.edu# By default, set workload to path of user-specified binary
1346391Sksewell@umich.eduworkloads = options.cmd
1356642Sksewell@umich.edunumThreads = 1
1366391Sksewell@umich.edu
1378649Snilay@cs.wisc.eduif options.cpu_type == "detailed" or options.cpu_type == "inorder":
1382833SN/A    #check for SMT workload
1392833SN/A    workloads = options.cmd.split(';')
1402833SN/A    if len(workloads) > 1:
1412833SN/A        process = []
1422833SN/A        smt_idx = 0
1432833SN/A        inputs = []
1445514SMichael.Adler@intel.com        outputs = []
1455514SMichael.Adler@intel.com        errouts = []
1462833SN/A
1472833SN/A        if options.input != "":
1482833SN/A            inputs = options.input.split(';')
1495514SMichael.Adler@intel.com        if options.output != "":
1505514SMichael.Adler@intel.com            outputs = options.output.split(';')
1515514SMichael.Adler@intel.com        if options.errout != "":
1525514SMichael.Adler@intel.com            errouts = options.errout.split(';')
1532833SN/A
1542833SN/A        for wrkld in workloads:
1552833SN/A            smt_process = LiveProcess()
1563005Sstever@eecs.umich.edu            smt_process.executable = wrkld
1572833SN/A            smt_process.cmd = wrkld + " " + options.options
1582833SN/A            if inputs and inputs[smt_idx]:
1592833SN/A                smt_process.input = inputs[smt_idx]
1605514SMichael.Adler@intel.com            if outputs and outputs[smt_idx]:
1615514SMichael.Adler@intel.com                smt_process.output = outputs[smt_idx]
1625514SMichael.Adler@intel.com            if errouts and errouts[smt_idx]:
1635514SMichael.Adler@intel.com                smt_process.errout = errouts[smt_idx]
1642833SN/A            process += [smt_process, ]
1652833SN/A            smt_idx += 1
1666642Sksewell@umich.edu    numThreads = len(workloads)
1676642Sksewell@umich.edu
1688169SLisa.Hsu@amd.comif options.ruby:
1698649Snilay@cs.wisc.edu    if options.cpu_type == "detailed":
1708169SLisa.Hsu@amd.com        print >> sys.stderr, "Ruby only works with TimingSimpleCPU!!"
1718169SLisa.Hsu@amd.com        sys.exit(1)
1728649Snilay@cs.wisc.edu    elif not options.cpu_type == "timing":
1738169SLisa.Hsu@amd.com        print >> sys.stderr, "****WARN:  using Timing CPU since it's needed by Ruby"
1748169SLisa.Hsu@amd.com
1758169SLisa.Hsu@amd.com    class CPUClass(TimingSimpleCPU): pass
1768169SLisa.Hsu@amd.com    test_mem_mode = 'timing'
1778169SLisa.Hsu@amd.com    FutureClass = None
1788169SLisa.Hsu@amd.comelse:
1798169SLisa.Hsu@amd.com    (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
1802957SN/A
1813395Shsul@eecs.umich.eduCPUClass.clock = '2GHz'
1826642Sksewell@umich.eduCPUClass.numThreads = numThreads;
1833005Sstever@eecs.umich.edu
1843395Shsul@eecs.umich.edunp = options.num_cpus
1853395Shsul@eecs.umich.edu
1863395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
1873323Shsul@eecs.umich.edu                physmem = PhysicalMemory(range=AddrRange("512MB")),
1883395Shsul@eecs.umich.edu                membus = Bus(), mem_mode = test_mem_mode)
1893395Shsul@eecs.umich.edu
1908169SLisa.Hsu@amd.comif options.ruby:
1918169SLisa.Hsu@amd.com    options.use_map = True
1928436SBrad.Beckmann@amd.com    Ruby.create_system(options, system)
1938322Ssteve.reinhardt@amd.com    assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
1948706Sandreas.hansson@arm.com    system.system_port = system.ruby._sys_port_proxy.port
1958169SLisa.Hsu@amd.comelse:
1968706Sandreas.hansson@arm.com    system.system_port = system.membus.port
1978169SLisa.Hsu@amd.com    system.physmem.port = system.membus.port
1988169SLisa.Hsu@amd.com    CacheConfig.config_cache(options, system)
1995056Ssaidi@eecs.umich.edu
2003395Shsul@eecs.umich.edufor i in xrange(np):
2018167SLisa.Hsu@amd.com    system.cpu[i].workload = multiprocesses[i]
2023005Sstever@eecs.umich.edu
2038169SLisa.Hsu@amd.com    if options.ruby:
2048322Ssteve.reinhardt@amd.com        system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
2058322Ssteve.reinhardt@amd.com        system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
2068169SLisa.Hsu@amd.com
2074968Sacolyte@umich.edu    if options.fastmem:
2084968Sacolyte@umich.edu        system.cpu[0].physmem_port = system.physmem.port
2094968Sacolyte@umich.edu
2103005Sstever@eecs.umich.eduroot = Root(system = system)
2112902SN/A
2123481Shsul@eecs.umich.eduSimulation.run(options, root, system, FutureClass)
213