se.py revision 6654
15369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan
23005Sstever@eecs.umich.edu# All rights reserved.
33005Sstever@eecs.umich.edu#
43005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
53005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
63005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
73005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
83005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
93005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
103005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution;
113005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its
123005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
133005Sstever@eecs.umich.edu# this software without specific prior written permission.
143005Sstever@eecs.umich.edu#
153005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
163005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
173005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
183005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
193005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
203005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
213005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
223005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
233005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
243005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
253005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
263005Sstever@eecs.umich.edu#
273005Sstever@eecs.umich.edu# Authors: Steve Reinhardt
283005Sstever@eecs.umich.edu
292710SN/A# Simple test script
302710SN/A#
313005Sstever@eecs.umich.edu# "m5 test.py"
322889SN/A
336654Snate@binkert.orgimport os
346654Snate@binkert.orgimport optparse
356654Snate@binkert.orgimport sys
366654Snate@binkert.orgfrom os.path import join as joinpath
376654Snate@binkert.org
382667SN/Aimport m5
396654Snate@binkert.orgfrom m5.defines import buildEnv
406654Snate@binkert.orgfrom m5.objects import *
416654Snate@binkert.orgfrom m5.util import addToPath, fatal
425457Ssaidi@eecs.umich.edu
436654Snate@binkert.orgif buildEnv['FULL_SYSTEM']:
446654Snate@binkert.org    fatal("This script requires syscall emulation mode (*_SE).")
455457Ssaidi@eecs.umich.edu
466654Snate@binkert.orgaddToPath('../common')
476654Snate@binkert.org
483395Shsul@eecs.umich.eduimport Simulation
493448Shsul@eecs.umich.edufrom Caches import *
505369Ssaidi@eecs.umich.edufrom cpu2000 import *
513394Shsul@eecs.umich.edu
523444Sktlim@umich.edu# Get paths we might need.  It's expected this file is in m5/configs/example.
533444Sktlim@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__))
543444Sktlim@umich.educonfig_root = os.path.dirname(config_path)
553444Sktlim@umich.edum5_root = os.path.dirname(config_root)
562424SN/A
572957SN/Aparser = optparse.OptionParser()
582957SN/A
593323Shsul@eecs.umich.edu# Benchmark options
603005Sstever@eecs.umich.eduparser.add_option("-c", "--cmd",
615514SMichael.Adler@intel.com    default=joinpath(m5_root, "tests/test-progs/hello/bin/alpha/linux/hello"),
625514SMichael.Adler@intel.com    help="The binary to run in syscall emulation mode.")
632957SN/Aparser.add_option("-o", "--options", default="",
645514SMichael.Adler@intel.com    help='The options to pass to the binary, use " " around the entire string')
655514SMichael.Adler@intel.comparser.add_option("-i", "--input", default="", help="Read stdin from a file.")
665514SMichael.Adler@intel.comparser.add_option("--output", default="", help="Redirect stdout to a file.")
675514SMichael.Adler@intel.comparser.add_option("--errout", default="", help="Redirect stderr to a file.")
683323Shsul@eecs.umich.edu
693444Sktlim@umich.eduexecfile(os.path.join(config_root, "common", "Options.py"))
702957SN/A
712957SN/A(options, args) = parser.parse_args()
722957SN/A
732957SN/Aif args:
742957SN/A    print "Error: script doesn't take any positional arguments"
752957SN/A    sys.exit(1)
762957SN/A
775369Ssaidi@eecs.umich.eduif options.bench:
785369Ssaidi@eecs.umich.edu    try:
796654Snate@binkert.org        if buildEnv['TARGET_ISA'] != 'alpha':
805369Ssaidi@eecs.umich.edu            print >>sys.stderr, "Simpoints code only works for Alpha ISA at this time"
815369Ssaidi@eecs.umich.edu            sys.exit(1)
825369Ssaidi@eecs.umich.edu        exec("workload = %s('alpha', 'tru64', 'ref')" % options.bench)
835369Ssaidi@eecs.umich.edu        process = workload.makeLiveProcess()
845369Ssaidi@eecs.umich.edu    except:
855369Ssaidi@eecs.umich.edu        print >>sys.stderr, "Unable to find workload for %s" % options.bench
865369Ssaidi@eecs.umich.edu        sys.exit(1)
875369Ssaidi@eecs.umich.eduelse:
885369Ssaidi@eecs.umich.edu    process = LiveProcess()
895369Ssaidi@eecs.umich.edu    process.executable = options.cmd
905369Ssaidi@eecs.umich.edu    process.cmd = [options.cmd] + options.options.split()
915369Ssaidi@eecs.umich.edu
925369Ssaidi@eecs.umich.edu
932801SN/Aif options.input != "":
942801SN/A    process.input = options.input
955514SMichael.Adler@intel.comif options.output != "":
965514SMichael.Adler@intel.com    process.output = options.output
975514SMichael.Adler@intel.comif options.errout != "":
985514SMichael.Adler@intel.com    process.errout = options.errout
992418SN/A
1006391Sksewell@umich.edu
1016391Sksewell@umich.edu# By default, set workload to path of user-specified binary
1026391Sksewell@umich.eduworkloads = options.cmd
1036642Sksewell@umich.edunumThreads = 1
1046391Sksewell@umich.edu
1056642Sksewell@umich.eduif options.detailed or options.inorder:
1062833SN/A    #check for SMT workload
1072833SN/A    workloads = options.cmd.split(';')
1082833SN/A    if len(workloads) > 1:
1092833SN/A        process = []
1102833SN/A        smt_idx = 0
1112833SN/A        inputs = []
1125514SMichael.Adler@intel.com        outputs = []
1135514SMichael.Adler@intel.com        errouts = []
1142833SN/A
1152833SN/A        if options.input != "":
1162833SN/A            inputs = options.input.split(';')
1175514SMichael.Adler@intel.com        if options.output != "":
1185514SMichael.Adler@intel.com            outputs = options.output.split(';')
1195514SMichael.Adler@intel.com        if options.errout != "":
1205514SMichael.Adler@intel.com            errouts = options.errout.split(';')
1212833SN/A
1222833SN/A        for wrkld in workloads:
1232833SN/A            smt_process = LiveProcess()
1243005Sstever@eecs.umich.edu            smt_process.executable = wrkld
1252833SN/A            smt_process.cmd = wrkld + " " + options.options
1262833SN/A            if inputs and inputs[smt_idx]:
1272833SN/A                smt_process.input = inputs[smt_idx]
1285514SMichael.Adler@intel.com            if outputs and outputs[smt_idx]:
1295514SMichael.Adler@intel.com                smt_process.output = outputs[smt_idx]
1305514SMichael.Adler@intel.com            if errouts and errouts[smt_idx]:
1315514SMichael.Adler@intel.com                smt_process.errout = errouts[smt_idx]
1322833SN/A            process += [smt_process, ]
1332833SN/A            smt_idx += 1
1346642Sksewell@umich.edu    numThreads = len(workloads)
1356642Sksewell@umich.edu
1363481Shsul@eecs.umich.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
1372957SN/A
1383395Shsul@eecs.umich.eduCPUClass.clock = '2GHz'
1396642Sksewell@umich.eduCPUClass.numThreads = numThreads;
1403005Sstever@eecs.umich.edu
1413395Shsul@eecs.umich.edunp = options.num_cpus
1423395Shsul@eecs.umich.edu
1433395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
1443323Shsul@eecs.umich.edu                physmem = PhysicalMemory(range=AddrRange("512MB")),
1453395Shsul@eecs.umich.edu                membus = Bus(), mem_mode = test_mem_mode)
1463395Shsul@eecs.umich.edu
1473005Sstever@eecs.umich.edusystem.physmem.port = system.membus.port
1483395Shsul@eecs.umich.edu
1495056Ssaidi@eecs.umich.eduif options.l2cache:
1505056Ssaidi@eecs.umich.edu    system.l2 = L2Cache(size='2MB')
1515056Ssaidi@eecs.umich.edu    system.tol2bus = Bus()
1525056Ssaidi@eecs.umich.edu    system.l2.cpu_side = system.tol2bus.port
1535056Ssaidi@eecs.umich.edu    system.l2.mem_side = system.membus.port
1545056Ssaidi@eecs.umich.edu
1553395Shsul@eecs.umich.edufor i in xrange(np):
1563514Sktlim@umich.edu    if options.caches:
1573395Shsul@eecs.umich.edu        system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
1583448Shsul@eecs.umich.edu                                              L1Cache(size = '64kB'))
1594455Ssaidi@eecs.umich.edu    if options.l2cache:
1604455Ssaidi@eecs.umich.edu        system.cpu[i].connectMemPorts(system.tol2bus)
1614455Ssaidi@eecs.umich.edu    else:
1624455Ssaidi@eecs.umich.edu        system.cpu[i].connectMemPorts(system.membus)
1633395Shsul@eecs.umich.edu    system.cpu[i].workload = process
1643005Sstever@eecs.umich.edu
1654968Sacolyte@umich.edu    if options.fastmem:
1664968Sacolyte@umich.edu        system.cpu[0].physmem_port = system.physmem.port
1674968Sacolyte@umich.edu
1683005Sstever@eecs.umich.eduroot = Root(system = system)
1692902SN/A
1703481Shsul@eecs.umich.eduSimulation.run(options, root, system, FutureClass)
171