se.py revision 12014
19793Sakash.bagdia@arm.com# Copyright (c) 2012-2013 ARM Limited
28706Sandreas.hansson@arm.com# All rights reserved.
38706Sandreas.hansson@arm.com#
48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall
58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual
68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating
78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software
88706Sandreas.hansson@arm.com# licensed hereunder.  You may use the software subject to the license
98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated
108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software,
118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form.
128706Sandreas.hansson@arm.com#
135369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan
143005Sstever@eecs.umich.edu# All rights reserved.
153005Sstever@eecs.umich.edu#
163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution;
233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its
243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
253005Sstever@eecs.umich.edu# this software without specific prior written permission.
263005Sstever@eecs.umich.edu#
273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
383005Sstever@eecs.umich.edu#
393005Sstever@eecs.umich.edu# Authors: Steve Reinhardt
403005Sstever@eecs.umich.edu
412710SN/A# Simple test script
422710SN/A#
433005Sstever@eecs.umich.edu# "m5 test.py"
442889SN/A
456654Snate@binkert.orgimport optparse
466654Snate@binkert.orgimport sys
479907Snilay@cs.wisc.eduimport os
486654Snate@binkert.org
492667SN/Aimport m5
506654Snate@binkert.orgfrom m5.defines import buildEnv
516654Snate@binkert.orgfrom m5.objects import *
526654Snate@binkert.orgfrom m5.util import addToPath, fatal
535457Ssaidi@eecs.umich.edu
5411670Sandreas.hansson@arm.comaddToPath('../')
5511670Sandreas.hansson@arm.com
5611670Sandreas.hansson@arm.comfrom ruby import Ruby
578169SLisa.Hsu@amd.com
5811682Sandreas.hansson@arm.comfrom common import Options
5911682Sandreas.hansson@arm.comfrom common import Simulation
6011682Sandreas.hansson@arm.comfrom common import CacheConfig
6111682Sandreas.hansson@arm.comfrom common import CpuConfig
6211682Sandreas.hansson@arm.comfrom common import MemConfig
6311682Sandreas.hansson@arm.comfrom common.Caches import *
6411682Sandreas.hansson@arm.comfrom common.cpu2000 import *
653394Shsul@eecs.umich.edu
6610555Salexandru.dutu@amd.com# Check if KVM support has been enabled, we might need to do VM
6710555Salexandru.dutu@amd.com# configuration if that's the case.
6810555Salexandru.dutu@amd.comhave_kvm_support = 'BaseKvmCPU' in globals()
6910555Salexandru.dutu@amd.comdef is_kvm_cpu(cpu_class):
7010555Salexandru.dutu@amd.com    return have_kvm_support and cpu_class != None and \
7110555Salexandru.dutu@amd.com        issubclass(cpu_class, BaseKvmCPU)
7210555Salexandru.dutu@amd.com
739197Snilay@cs.wisc.edudef get_processes(options):
749197Snilay@cs.wisc.edu    """Interprets provided options and returns a list of processes"""
759197Snilay@cs.wisc.edu
769197Snilay@cs.wisc.edu    multiprocesses = []
779197Snilay@cs.wisc.edu    inputs = []
789197Snilay@cs.wisc.edu    outputs = []
799197Snilay@cs.wisc.edu    errouts = []
809197Snilay@cs.wisc.edu    pargs = []
819197Snilay@cs.wisc.edu
829197Snilay@cs.wisc.edu    workloads = options.cmd.split(';')
839197Snilay@cs.wisc.edu    if options.input != "":
849197Snilay@cs.wisc.edu        inputs = options.input.split(';')
859197Snilay@cs.wisc.edu    if options.output != "":
869197Snilay@cs.wisc.edu        outputs = options.output.split(';')
879197Snilay@cs.wisc.edu    if options.errout != "":
889197Snilay@cs.wisc.edu        errouts = options.errout.split(';')
899197Snilay@cs.wisc.edu    if options.options != "":
909197Snilay@cs.wisc.edu        pargs = options.options.split(';')
919197Snilay@cs.wisc.edu
929197Snilay@cs.wisc.edu    idx = 0
939197Snilay@cs.wisc.edu    for wrkld in workloads:
9411851Sbrandon.potter@amd.com        process = Process()
959197Snilay@cs.wisc.edu        process.executable = wrkld
969907Snilay@cs.wisc.edu        process.cwd = os.getcwd()
979197Snilay@cs.wisc.edu
9810803Sbrandon.potter@amd.com        if options.env:
9910803Sbrandon.potter@amd.com            with open(options.env, 'r') as f:
10010803Sbrandon.potter@amd.com                process.env = [line.rstrip() for line in f]
10110803Sbrandon.potter@amd.com
1029197Snilay@cs.wisc.edu        if len(pargs) > idx:
1039217Snilay@cs.wisc.edu            process.cmd = [wrkld] + pargs[idx].split()
1049197Snilay@cs.wisc.edu        else:
1059197Snilay@cs.wisc.edu            process.cmd = [wrkld]
1069197Snilay@cs.wisc.edu
1079197Snilay@cs.wisc.edu        if len(inputs) > idx:
1089197Snilay@cs.wisc.edu            process.input = inputs[idx]
1099197Snilay@cs.wisc.edu        if len(outputs) > idx:
1109197Snilay@cs.wisc.edu            process.output = outputs[idx]
1119197Snilay@cs.wisc.edu        if len(errouts) > idx:
1129197Snilay@cs.wisc.edu            process.errout = errouts[idx]
1139197Snilay@cs.wisc.edu
1149197Snilay@cs.wisc.edu        multiprocesses.append(process)
1159197Snilay@cs.wisc.edu        idx += 1
1169197Snilay@cs.wisc.edu
1179197Snilay@cs.wisc.edu    if options.smt:
11812014Sgabeblack@google.com        assert(options.cpu_type == "DerivO3CPU")
1199197Snilay@cs.wisc.edu        return multiprocesses, idx
1209197Snilay@cs.wisc.edu    else:
1219197Snilay@cs.wisc.edu        return multiprocesses, 1
1229197Snilay@cs.wisc.edu
1239197Snilay@cs.wisc.edu
1242957SN/Aparser = optparse.OptionParser()
1258920Snilay@cs.wisc.eduOptions.addCommonOptions(parser)
1268920Snilay@cs.wisc.eduOptions.addSEOptions(parser)
1272957SN/A
1288862Snilay@cs.wisc.eduif '--ruby' in sys.argv:
1298862Snilay@cs.wisc.edu    Ruby.define_options(parser)
1308467Snilay@cs.wisc.edu
1312957SN/A(options, args) = parser.parse_args()
1322957SN/A
1332957SN/Aif args:
1342957SN/A    print "Error: script doesn't take any positional arguments"
1352957SN/A    sys.exit(1)
1362957SN/A
1378167SLisa.Hsu@amd.commultiprocesses = []
1389197Snilay@cs.wisc.edunumThreads = 1
1398167SLisa.Hsu@amd.com
1405369Ssaidi@eecs.umich.eduif options.bench:
1418167SLisa.Hsu@amd.com    apps = options.bench.split("-")
1428167SLisa.Hsu@amd.com    if len(apps) != options.num_cpus:
1438167SLisa.Hsu@amd.com        print "number of benchmarks not equal to set num_cpus!"
1448167SLisa.Hsu@amd.com        sys.exit(1)
1458167SLisa.Hsu@amd.com
1468167SLisa.Hsu@amd.com    for app in apps:
1478167SLisa.Hsu@amd.com        try:
1488168SLisa.Hsu@amd.com            if buildEnv['TARGET_ISA'] == 'alpha':
14910037SARM gem5 Developers                exec("workload = %s('alpha', 'tru64', '%s')" % (
15010037SARM gem5 Developers                        app, options.spec_input))
15110037SARM gem5 Developers            elif buildEnv['TARGET_ISA'] == 'arm':
15210037SARM gem5 Developers                exec("workload = %s('arm_%s', 'linux', '%s')" % (
15310037SARM gem5 Developers                        app, options.arm_iset, options.spec_input))
1548168SLisa.Hsu@amd.com            else:
15510037SARM gem5 Developers                exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
15610037SARM gem5 Developers                        app, options.spec_input))
15711851Sbrandon.potter@amd.com            multiprocesses.append(workload.makeProcess())
1588167SLisa.Hsu@amd.com        except:
15910118Snilay@cs.wisc.edu            print >>sys.stderr, "Unable to find workload for %s: %s" % (
16010118Snilay@cs.wisc.edu                    buildEnv['TARGET_ISA'], app)
1615369Ssaidi@eecs.umich.edu            sys.exit(1)
1628920Snilay@cs.wisc.eduelif options.cmd:
1639197Snilay@cs.wisc.edu    multiprocesses, numThreads = get_processes(options)
1648920Snilay@cs.wisc.eduelse:
1658920Snilay@cs.wisc.edu    print >> sys.stderr, "No workload specified. Exiting!\n"
1668920Snilay@cs.wisc.edu    sys.exit(1)
1675369Ssaidi@eecs.umich.edu
1685369Ssaidi@eecs.umich.edu
1698718Snilay@cs.wisc.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
1709197Snilay@cs.wisc.eduCPUClass.numThreads = numThreads
1719197Snilay@cs.wisc.edu
1729197Snilay@cs.wisc.edu# Check -- do not allow SMT with multiple CPUs
1739197Snilay@cs.wisc.eduif options.smt and options.num_cpus > 1:
1749197Snilay@cs.wisc.edu    fatal("You cannot use SMT with multiple CPUs!")
1753005Sstever@eecs.umich.edu
1763395Shsul@eecs.umich.edunp = options.num_cpus
1773395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
1789793Sakash.bagdia@arm.com                mem_mode = test_mem_mode,
1799836Sandreas.hansson@arm.com                mem_ranges = [AddrRange(options.mem_size)],
1809815SAndreas Hansson <andreas.hansson>                cache_line_size = options.cacheline_size)
1819793Sakash.bagdia@arm.com
18211147Smitch.hayenga@arm.comif numThreads > 1:
18311147Smitch.hayenga@arm.com    system.multi_thread = True
18411147Smitch.hayenga@arm.com
1859827Sakash.bagdia@arm.com# Create a top-level voltage domain
1869827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
1879827Sakash.bagdia@arm.com
1889827Sakash.bagdia@arm.com# Create a source clock for the system and set the clock period
1899827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock =  options.sys_clock,
1909827Sakash.bagdia@arm.com                                   voltage_domain = system.voltage_domain)
1919827Sakash.bagdia@arm.com
1929827Sakash.bagdia@arm.com# Create a CPU voltage domain
1939827Sakash.bagdia@arm.comsystem.cpu_voltage_domain = VoltageDomain()
1949827Sakash.bagdia@arm.com
1959793Sakash.bagdia@arm.com# Create a separate clock domain for the CPUs
1969827Sakash.bagdia@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
1979827Sakash.bagdia@arm.com                                       voltage_domain =
1989827Sakash.bagdia@arm.com                                       system.cpu_voltage_domain)
1999793Sakash.bagdia@arm.com
20011251Sradhika.jagtap@ARM.com# If elastic tracing is enabled, then configure the cpu and attach the elastic
20111251Sradhika.jagtap@ARM.com# trace probe
20211251Sradhika.jagtap@ARM.comif options.elastic_trace_en:
20311251Sradhika.jagtap@ARM.com    CpuConfig.config_etrace(CPUClass, system.cpu, options)
20411251Sradhika.jagtap@ARM.com
2059793Sakash.bagdia@arm.com# All cpus belong to a common cpu_clk_domain, therefore running at a common
2069793Sakash.bagdia@arm.com# frequency.
2079793Sakash.bagdia@arm.comfor cpu in system.cpu:
2089793Sakash.bagdia@arm.com    cpu.clk_domain = system.cpu_clk_domain
2093395Shsul@eecs.umich.edu
21010555Salexandru.dutu@amd.comif is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass):
21110555Salexandru.dutu@amd.com    if buildEnv['TARGET_ISA'] == 'x86':
21211839SCurtis.Dunham@arm.com        system.kvm_vm = KvmVM()
21310555Salexandru.dutu@amd.com        for process in multiprocesses:
21410555Salexandru.dutu@amd.com            process.useArchPT = True
21510555Salexandru.dutu@amd.com            process.kvmInSE = True
21610555Salexandru.dutu@amd.com    else:
21710555Salexandru.dutu@amd.com        fatal("KvmCPU can only be used in SE mode with x86")
21810555Salexandru.dutu@amd.com
2198926Sandreas.hansson@arm.com# Sanity check
2209317Sandreas.hansson@arm.comif options.fastmem:
2219317Sandreas.hansson@arm.com    if CPUClass != AtomicSimpleCPU:
2229317Sandreas.hansson@arm.com        fatal("Fastmem can only be used with atomic CPU!")
2239317Sandreas.hansson@arm.com    if (options.caches or options.l2cache):
2249317Sandreas.hansson@arm.com        fatal("You cannot use fastmem in combination with caches!")
2258926Sandreas.hansson@arm.com
2269647Sdam.sunwoo@arm.comif options.simpoint_profile:
2279647Sdam.sunwoo@arm.com    if not options.fastmem:
2289647Sdam.sunwoo@arm.com        # Atomic CPU checked with fastmem option already
2299647Sdam.sunwoo@arm.com        fatal("SimPoint generation should be done with atomic cpu and fastmem")
2309647Sdam.sunwoo@arm.com    if np > 1:
2319647Sdam.sunwoo@arm.com        fatal("SimPoint generation not supported with more than one CPUs")
2329647Sdam.sunwoo@arm.com
2333395Shsul@eecs.umich.edufor i in xrange(np):
2349197Snilay@cs.wisc.edu    if options.smt:
2359197Snilay@cs.wisc.edu        system.cpu[i].workload = multiprocesses
2369197Snilay@cs.wisc.edu    elif len(multiprocesses) == 1:
2378957Sjayneel@cs.wisc.edu        system.cpu[i].workload = multiprocesses[0]
2388957Sjayneel@cs.wisc.edu    else:
2398957Sjayneel@cs.wisc.edu        system.cpu[i].workload = multiprocesses[i]
2403005Sstever@eecs.umich.edu
2414968Sacolyte@umich.edu    if options.fastmem:
2429006Sandreas.hansson@arm.com        system.cpu[i].fastmem = True
2434968Sacolyte@umich.edu
2449647Sdam.sunwoo@arm.com    if options.simpoint_profile:
24510381Sdam.sunwoo@arm.com        system.cpu[i].addSimPointProbe(options.simpoint_interval)
2469647Sdam.sunwoo@arm.com
2478887Sgeoffrey.blake@arm.com    if options.checker:
2488887Sgeoffrey.blake@arm.com        system.cpu[i].addCheckerCpu()
2498887Sgeoffrey.blake@arm.com
2509384SAndreas.Sandberg@arm.com    system.cpu[i].createThreads()
2519384SAndreas.Sandberg@arm.com
2528887Sgeoffrey.blake@arm.comif options.ruby:
25311995Sgabeblack@google.com    if options.cpu_type == "AtomicSimpleCPU":
25411088Snilay@cs.wisc.edu        print >> sys.stderr, "Ruby does not work with atomic cpu!!"
2558896Snilay@cs.wisc.edu        sys.exit(1)
2568896Snilay@cs.wisc.edu
25710519Snilay@cs.wisc.edu    Ruby.create_system(options, False, system)
25810120Snilay@cs.wisc.edu    assert(options.num_cpus == len(system.ruby._cpu_ports))
2598896Snilay@cs.wisc.edu
26010300Scastilloe@unican.es    system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
26110300Scastilloe@unican.es                                        voltage_domain = system.voltage_domain)
2628896Snilay@cs.wisc.edu    for i in xrange(np):
26310120Snilay@cs.wisc.edu        ruby_port = system.ruby._cpu_ports[i]
2648896Snilay@cs.wisc.edu
2658896Snilay@cs.wisc.edu        # Create the interrupt controller and connect its ports to Ruby
2669268Smalek.musleh@gmail.com        # Note that the interrupt controller is always present but only
2679268Smalek.musleh@gmail.com        # in x86 does it have message ports that need to be connected
2688896Snilay@cs.wisc.edu        system.cpu[i].createInterruptController()
2698896Snilay@cs.wisc.edu
2708896Snilay@cs.wisc.edu        # Connect the cpu's cache ports to Ruby
2718896Snilay@cs.wisc.edu        system.cpu[i].icache_port = ruby_port.slave
2728896Snilay@cs.wisc.edu        system.cpu[i].dcache_port = ruby_port.slave
2739222Shestness@cs.wisc.edu        if buildEnv['TARGET_ISA'] == 'x86':
27411150Smitch.hayenga@arm.com            system.cpu[i].interrupts[0].pio = ruby_port.master
27511150Smitch.hayenga@arm.com            system.cpu[i].interrupts[0].int_master = ruby_port.slave
27611150Smitch.hayenga@arm.com            system.cpu[i].interrupts[0].int_slave = ruby_port.master
2779222Shestness@cs.wisc.edu            system.cpu[i].itb.walker.port = ruby_port.slave
2789222Shestness@cs.wisc.edu            system.cpu[i].dtb.walker.port = ruby_port.slave
2798887Sgeoffrey.blake@arm.comelse:
28010150Snilay@cs.wisc.edu    MemClass = Simulation.setMemClass(options)
28110720Sandreas.hansson@arm.com    system.membus = SystemXBar()
2828887Sgeoffrey.blake@arm.com    system.system_port = system.membus.slave
2838887Sgeoffrey.blake@arm.com    CacheConfig.config_cache(options, system)
2849836Sandreas.hansson@arm.com    MemConfig.config_mem(options, system)
2858887Sgeoffrey.blake@arm.com
2868801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system)
2873481Shsul@eecs.umich.eduSimulation.run(options, root, system, FutureClass)
288