se.py revision 11670 
1# Copyright (c) 2012-2013 ARM Limited
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13# Copyright (c) 2006-2008 The Regents of The University of Michigan
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38#
39# Authors: Steve Reinhardt
40
41# Simple test script
42#
43# "m5 test.py"
44
45import optparse
46import sys
47import os
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal
53
54addToPath('../')
55addToPath('../common')
56
57from ruby import Ruby
58
59import Options
60import Simulation
61import CacheConfig
62import CpuConfig
63import MemConfig
64from Caches import *
65from cpu2000 import *
66
67# Check if KVM support has been enabled, we might need to do VM
68# configuration if that's the case.
69have_kvm_support = 'BaseKvmCPU' in globals()
70def is_kvm_cpu(cpu_class):
71    return have_kvm_support and cpu_class != None and \
72        issubclass(cpu_class, BaseKvmCPU)
73
74def get_processes(options):
75    """Interprets provided options and returns a list of processes"""
76
77    multiprocesses = []
78    inputs = []
79    outputs = []
80    errouts = []
81    pargs = []
82
83    workloads = options.cmd.split(';')
84    if options.input != "":
85        inputs = options.input.split(';')
86    if options.output != "":
87        outputs = options.output.split(';')
88    if options.errout != "":
89        errouts = options.errout.split(';')
90    if options.options != "":
91        pargs = options.options.split(';')
92
93    idx = 0
94    for wrkld in workloads:
95        process = LiveProcess()
96        process.executable = wrkld
97        process.cwd = os.getcwd()
98
99        if options.env:
100            with open(options.env, 'r') as f:
101                process.env = [line.rstrip() for line in f]
102
103        if len(pargs) > idx:
104            process.cmd = [wrkld] + pargs[idx].split()
105        else:
106            process.cmd = [wrkld]
107
108        if len(inputs) > idx:
109            process.input = inputs[idx]
110        if len(outputs) > idx:
111            process.output = outputs[idx]
112        if len(errouts) > idx:
113            process.errout = errouts[idx]
114
115        multiprocesses.append(process)
116        idx += 1
117
118    if options.smt:
119        assert(options.cpu_type == "detailed")
120        return multiprocesses, idx
121    else:
122        return multiprocesses, 1
123
124
125parser = optparse.OptionParser()
126Options.addCommonOptions(parser)
127Options.addSEOptions(parser)
128
129if '--ruby' in sys.argv:
130    Ruby.define_options(parser)
131
132(options, args) = parser.parse_args()
133
134if args:
135    print "Error: script doesn't take any positional arguments"
136    sys.exit(1)
137
138multiprocesses = []
139numThreads = 1
140
141if options.bench:
142    apps = options.bench.split("-")
143    if len(apps) != options.num_cpus:
144        print "number of benchmarks not equal to set num_cpus!"
145        sys.exit(1)
146
147    for app in apps:
148        try:
149            if buildEnv['TARGET_ISA'] == 'alpha':
150                exec("workload = %s('alpha', 'tru64', '%s')" % (
151                        app, options.spec_input))
152            elif buildEnv['TARGET_ISA'] == 'arm':
153                exec("workload = %s('arm_%s', 'linux', '%s')" % (
154                        app, options.arm_iset, options.spec_input))
155            else:
156                exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
157                        app, options.spec_input))
158            multiprocesses.append(workload.makeLiveProcess())
159        except:
160            print >>sys.stderr, "Unable to find workload for %s: %s" % (
161                    buildEnv['TARGET_ISA'], app)
162            sys.exit(1)
163elif options.cmd:
164    multiprocesses, numThreads = get_processes(options)
165else:
166    print >> sys.stderr, "No workload specified. Exiting!\n"
167    sys.exit(1)
168
169
170(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
171CPUClass.numThreads = numThreads
172
173# Check -- do not allow SMT with multiple CPUs
174if options.smt and options.num_cpus > 1:
175    fatal("You cannot use SMT with multiple CPUs!")
176
177np = options.num_cpus
178system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
179                mem_mode = test_mem_mode,
180                mem_ranges = [AddrRange(options.mem_size)],
181                cache_line_size = options.cacheline_size)
182
183if numThreads > 1:
184    system.multi_thread = True
185
186# Create a top-level voltage domain
187system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
188
189# Create a source clock for the system and set the clock period
190system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
191                                   voltage_domain = system.voltage_domain)
192
193# Create a CPU voltage domain
194system.cpu_voltage_domain = VoltageDomain()
195
196# Create a separate clock domain for the CPUs
197system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
198                                       voltage_domain =
199                                       system.cpu_voltage_domain)
200
201# If elastic tracing is enabled, then configure the cpu and attach the elastic
202# trace probe
203if options.elastic_trace_en:
204    CpuConfig.config_etrace(CPUClass, system.cpu, options)
205
206# All cpus belong to a common cpu_clk_domain, therefore running at a common
207# frequency.
208for cpu in system.cpu:
209    cpu.clk_domain = system.cpu_clk_domain
210
211if is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass):
212    if buildEnv['TARGET_ISA'] == 'x86':
213        system.vm = KvmVM()
214        for process in multiprocesses:
215            process.useArchPT = True
216            process.kvmInSE = True
217    else:
218        fatal("KvmCPU can only be used in SE mode with x86")
219
220# Sanity check
221if options.fastmem:
222    if CPUClass != AtomicSimpleCPU:
223        fatal("Fastmem can only be used with atomic CPU!")
224    if (options.caches or options.l2cache):
225        fatal("You cannot use fastmem in combination with caches!")
226
227if options.simpoint_profile:
228    if not options.fastmem:
229        # Atomic CPU checked with fastmem option already
230        fatal("SimPoint generation should be done with atomic cpu and fastmem")
231    if np > 1:
232        fatal("SimPoint generation not supported with more than one CPUs")
233
234for i in xrange(np):
235    if options.smt:
236        system.cpu[i].workload = multiprocesses
237    elif len(multiprocesses) == 1:
238        system.cpu[i].workload = multiprocesses[0]
239    else:
240        system.cpu[i].workload = multiprocesses[i]
241
242    if options.fastmem:
243        system.cpu[i].fastmem = True
244
245    if options.simpoint_profile:
246        system.cpu[i].addSimPointProbe(options.simpoint_interval)
247
248    if options.checker:
249        system.cpu[i].addCheckerCpu()
250
251    system.cpu[i].createThreads()
252
253if options.ruby:
254    if options.cpu_type == "atomic" or options.cpu_type == "AtomicSimpleCPU":
255        print >> sys.stderr, "Ruby does not work with atomic cpu!!"
256        sys.exit(1)
257
258    Ruby.create_system(options, False, system)
259    assert(options.num_cpus == len(system.ruby._cpu_ports))
260
261    system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
262                                        voltage_domain = system.voltage_domain)
263    for i in xrange(np):
264        ruby_port = system.ruby._cpu_ports[i]
265
266        # Create the interrupt controller and connect its ports to Ruby
267        # Note that the interrupt controller is always present but only
268        # in x86 does it have message ports that need to be connected
269        system.cpu[i].createInterruptController()
270
271        # Connect the cpu's cache ports to Ruby
272        system.cpu[i].icache_port = ruby_port.slave
273        system.cpu[i].dcache_port = ruby_port.slave
274        if buildEnv['TARGET_ISA'] == 'x86':
275            system.cpu[i].interrupts[0].pio = ruby_port.master
276            system.cpu[i].interrupts[0].int_master = ruby_port.slave
277            system.cpu[i].interrupts[0].int_slave = ruby_port.master
278            system.cpu[i].itb.walker.port = ruby_port.slave
279            system.cpu[i].dtb.walker.port = ruby_port.slave
280else:
281    MemClass = Simulation.setMemClass(options)
282    system.membus = SystemXBar()
283    system.system_port = system.membus.slave
284    CacheConfig.config_cache(options, system)
285    MemConfig.config_mem(options, system)
286
287root = Root(full_system = False, system = system)
288Simulation.run(options, root, system, FutureClass)
289