se.py revision 11147
111936Sandreas.sandberg@arm.com# Copyright (c) 2012-2013 ARM Limited 211569Sgabor.dozsa@arm.com# All rights reserved. 311569Sgabor.dozsa@arm.com# 411569Sgabor.dozsa@arm.com# The license below extends only to copyright in the software and shall 511569Sgabor.dozsa@arm.com# not be construed as granting a license to any other intellectual 611569Sgabor.dozsa@arm.com# property including but not limited to intellectual property relating 711569Sgabor.dozsa@arm.com# to a hardware implementation of the functionality of the software 811569Sgabor.dozsa@arm.com# licensed hereunder. You may use the software subject to the license 911569Sgabor.dozsa@arm.com# terms below provided that you ensure that this notice is replicated 1011569Sgabor.dozsa@arm.com# unmodified and in its entirety in all distributions of the software, 1111569Sgabor.dozsa@arm.com# modified or unmodified, in source code or in binary form. 1211569Sgabor.dozsa@arm.com# 1311569Sgabor.dozsa@arm.com# Copyright (c) 2006-2008 The Regents of The University of Michigan 1411569Sgabor.dozsa@arm.com# All rights reserved. 1511569Sgabor.dozsa@arm.com# 1611569Sgabor.dozsa@arm.com# Redistribution and use in source and binary forms, with or without 1711569Sgabor.dozsa@arm.com# modification, are permitted provided that the following conditions are 1811569Sgabor.dozsa@arm.com# met: redistributions of source code must retain the above copyright 1911569Sgabor.dozsa@arm.com# notice, this list of conditions and the following disclaimer; 2011569Sgabor.dozsa@arm.com# redistributions in binary form must reproduce the above copyright 2111569Sgabor.dozsa@arm.com# notice, this list of conditions and the following disclaimer in the 2211569Sgabor.dozsa@arm.com# documentation and/or other materials provided with the distribution; 2311569Sgabor.dozsa@arm.com# neither the name of the copyright holders nor the names of its 2411569Sgabor.dozsa@arm.com# contributors may be used to endorse or promote products derived from 2511569Sgabor.dozsa@arm.com# this software without specific prior written permission. 2611569Sgabor.dozsa@arm.com# 2711569Sgabor.dozsa@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2811569Sgabor.dozsa@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2911569Sgabor.dozsa@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3011569Sgabor.dozsa@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3111569Sgabor.dozsa@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3211569Sgabor.dozsa@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3311569Sgabor.dozsa@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3411569Sgabor.dozsa@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3511569Sgabor.dozsa@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3611569Sgabor.dozsa@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3711569Sgabor.dozsa@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3811569Sgabor.dozsa@arm.com# 3911569Sgabor.dozsa@arm.com# Authors: Steve Reinhardt 4011569Sgabor.dozsa@arm.com 4111569Sgabor.dozsa@arm.com# Simple test script 4211569Sgabor.dozsa@arm.com# 4311682Sandreas.hansson@arm.com# "m5 test.py" 4411682Sandreas.hansson@arm.com 4511682Sandreas.hansson@arm.comimport optparse 4611569Sgabor.dozsa@arm.comimport sys 4712165Sandreas.sandberg@arm.comimport os 4811936Sandreas.sandberg@arm.com 4911569Sgabor.dozsa@arm.comimport m5 5011722Ssophiane.senni@gmail.comfrom m5.defines import buildEnv 5111722Ssophiane.senni@gmail.comfrom m5.objects import * 5211569Sgabor.dozsa@arm.comfrom m5.util import addToPath, fatal 5311569Sgabor.dozsa@arm.com 5411569Sgabor.dozsa@arm.comaddToPath('../common') 5511569Sgabor.dozsa@arm.comaddToPath('../ruby') 5611569Sgabor.dozsa@arm.com 5711569Sgabor.dozsa@arm.comimport Options 5811569Sgabor.dozsa@arm.comimport Ruby 5911569Sgabor.dozsa@arm.comimport Simulation 6011722Ssophiane.senni@gmail.comimport CacheConfig 6111722Ssophiane.senni@gmail.comimport MemConfig 6211569Sgabor.dozsa@arm.comfrom Caches import * 6311569Sgabor.dozsa@arm.comfrom cpu2000 import * 6411569Sgabor.dozsa@arm.com 6511569Sgabor.dozsa@arm.com# Check if KVM support has been enabled, we might need to do VM 6611569Sgabor.dozsa@arm.com# configuration if that's the case. 6711569Sgabor.dozsa@arm.comhave_kvm_support = 'BaseKvmCPU' in globals() 6811569Sgabor.dozsa@arm.comdef is_kvm_cpu(cpu_class): 6911569Sgabor.dozsa@arm.com return have_kvm_support and cpu_class != None and \ 7011569Sgabor.dozsa@arm.com issubclass(cpu_class, BaseKvmCPU) 7111722Ssophiane.senni@gmail.com 7211722Ssophiane.senni@gmail.comdef get_processes(options): 7311569Sgabor.dozsa@arm.com """Interprets provided options and returns a list of processes""" 7411569Sgabor.dozsa@arm.com 7511569Sgabor.dozsa@arm.com multiprocesses = [] 7611569Sgabor.dozsa@arm.com inputs = [] 7711569Sgabor.dozsa@arm.com outputs = [] 7811569Sgabor.dozsa@arm.com errouts = [] 7911569Sgabor.dozsa@arm.com pargs = [] 8011569Sgabor.dozsa@arm.com 8111569Sgabor.dozsa@arm.com workloads = options.cmd.split(';') 8211722Ssophiane.senni@gmail.com if options.input != "": 8311722Ssophiane.senni@gmail.com inputs = options.input.split(';') 8411569Sgabor.dozsa@arm.com if options.output != "": 8511569Sgabor.dozsa@arm.com outputs = options.output.split(';') 8611569Sgabor.dozsa@arm.com if options.errout != "": 8711569Sgabor.dozsa@arm.com errouts = options.errout.split(';') 8811569Sgabor.dozsa@arm.com if options.options != "": 8911569Sgabor.dozsa@arm.com pargs = options.options.split(';') 9011569Sgabor.dozsa@arm.com 9111569Sgabor.dozsa@arm.com idx = 0 9211569Sgabor.dozsa@arm.com for wrkld in workloads: 9311569Sgabor.dozsa@arm.com process = LiveProcess() 9411569Sgabor.dozsa@arm.com process.executable = wrkld 9511569Sgabor.dozsa@arm.com process.cwd = os.getcwd() 9611722Ssophiane.senni@gmail.com 9711722Ssophiane.senni@gmail.com if options.env: 9811569Sgabor.dozsa@arm.com with open(options.env, 'r') as f: 9911569Sgabor.dozsa@arm.com process.env = [line.rstrip() for line in f] 10011569Sgabor.dozsa@arm.com 10111569Sgabor.dozsa@arm.com if len(pargs) > idx: 10211569Sgabor.dozsa@arm.com process.cmd = [wrkld] + pargs[idx].split() 10311569Sgabor.dozsa@arm.com else: 10411569Sgabor.dozsa@arm.com process.cmd = [wrkld] 10511569Sgabor.dozsa@arm.com 10611569Sgabor.dozsa@arm.com if len(inputs) > idx: 10711569Sgabor.dozsa@arm.com process.input = inputs[idx] 10811569Sgabor.dozsa@arm.com if len(outputs) > idx: 10911630Sgabor.dozsa@arm.com process.output = outputs[idx] 11011630Sgabor.dozsa@arm.com if len(errouts) > idx: 11111630Sgabor.dozsa@arm.com process.errout = errouts[idx] 11211630Sgabor.dozsa@arm.com 11311630Sgabor.dozsa@arm.com multiprocesses.append(process) 11411630Sgabor.dozsa@arm.com idx += 1 11511630Sgabor.dozsa@arm.com 11611630Sgabor.dozsa@arm.com if options.smt: 11711630Sgabor.dozsa@arm.com assert(options.cpu_type == "detailed") 11811630Sgabor.dozsa@arm.com return multiprocesses, idx 11911630Sgabor.dozsa@arm.com else: 12011630Sgabor.dozsa@arm.com return multiprocesses, 1 12111630Sgabor.dozsa@arm.com 12211630Sgabor.dozsa@arm.com 12311630Sgabor.dozsa@arm.comparser = optparse.OptionParser() 12411630Sgabor.dozsa@arm.comOptions.addCommonOptions(parser) 12511630Sgabor.dozsa@arm.comOptions.addSEOptions(parser) 12611630Sgabor.dozsa@arm.com 12711630Sgabor.dozsa@arm.comif '--ruby' in sys.argv: 12811630Sgabor.dozsa@arm.com Ruby.define_options(parser) 12911630Sgabor.dozsa@arm.com 13011630Sgabor.dozsa@arm.com(options, args) = parser.parse_args() 13111630Sgabor.dozsa@arm.com 13211630Sgabor.dozsa@arm.comif args: 13311630Sgabor.dozsa@arm.com print "Error: script doesn't take any positional arguments" 13411630Sgabor.dozsa@arm.com sys.exit(1) 13511630Sgabor.dozsa@arm.com 13611630Sgabor.dozsa@arm.commultiprocesses = [] 13711630Sgabor.dozsa@arm.comnumThreads = 1 13811630Sgabor.dozsa@arm.com 13911630Sgabor.dozsa@arm.comif options.bench: 14011630Sgabor.dozsa@arm.com apps = options.bench.split("-") 14111630Sgabor.dozsa@arm.com if len(apps) != options.num_cpus: 14211630Sgabor.dozsa@arm.com print "number of benchmarks not equal to set num_cpus!" 14311630Sgabor.dozsa@arm.com sys.exit(1) 14411630Sgabor.dozsa@arm.com 14511630Sgabor.dozsa@arm.com for app in apps: 14611630Sgabor.dozsa@arm.com try: 14711630Sgabor.dozsa@arm.com if buildEnv['TARGET_ISA'] == 'alpha': 14811630Sgabor.dozsa@arm.com exec("workload = %s('alpha', 'tru64', '%s')" % ( 14911630Sgabor.dozsa@arm.com app, options.spec_input)) 15011630Sgabor.dozsa@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 15111630Sgabor.dozsa@arm.com exec("workload = %s('arm_%s', 'linux', '%s')" % ( 15211630Sgabor.dozsa@arm.com app, options.arm_iset, options.spec_input)) 15311630Sgabor.dozsa@arm.com else: 15411630Sgabor.dozsa@arm.com exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % ( 15511630Sgabor.dozsa@arm.com app, options.spec_input)) 15611630Sgabor.dozsa@arm.com multiprocesses.append(workload.makeLiveProcess()) 15711630Sgabor.dozsa@arm.com except: 15811630Sgabor.dozsa@arm.com print >>sys.stderr, "Unable to find workload for %s: %s" % ( 15911630Sgabor.dozsa@arm.com buildEnv['TARGET_ISA'], app) 16011630Sgabor.dozsa@arm.com sys.exit(1) 16111630Sgabor.dozsa@arm.comelif options.cmd: 16211630Sgabor.dozsa@arm.com multiprocesses, numThreads = get_processes(options) 16311630Sgabor.dozsa@arm.comelse: 16411630Sgabor.dozsa@arm.com print >> sys.stderr, "No workload specified. Exiting!\n" 16511630Sgabor.dozsa@arm.com sys.exit(1) 16611630Sgabor.dozsa@arm.com 16711630Sgabor.dozsa@arm.com 16811630Sgabor.dozsa@arm.com(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 16912165Sandreas.sandberg@arm.comCPUClass.numThreads = numThreads 17011630Sgabor.dozsa@arm.com 17111630Sgabor.dozsa@arm.com# Check -- do not allow SMT with multiple CPUs 17211630Sgabor.dozsa@arm.comif options.smt and options.num_cpus > 1: 17311630Sgabor.dozsa@arm.com fatal("You cannot use SMT with multiple CPUs!") 17411630Sgabor.dozsa@arm.com 17511936Sandreas.sandberg@arm.comnp = options.num_cpus 17611936Sandreas.sandberg@arm.comsystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)], 17712165Sandreas.sandberg@arm.com mem_mode = test_mem_mode, 17811936Sandreas.sandberg@arm.com mem_ranges = [AddrRange(options.mem_size)], 17911936Sandreas.sandberg@arm.com cache_line_size = options.cacheline_size) 18011936Sandreas.sandberg@arm.com 18111936Sandreas.sandberg@arm.comif numThreads > 1: 18211936Sandreas.sandberg@arm.com system.multi_thread = True 18311630Sgabor.dozsa@arm.com 18411569Sgabor.dozsa@arm.com# Create a top-level voltage domain 18511569Sgabor.dozsa@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 18611569Sgabor.dozsa@arm.com 18711756Sgabor.dozsa@arm.com# Create a source clock for the system and set the clock period 18811630Sgabor.dozsa@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 18911569Sgabor.dozsa@arm.com voltage_domain = system.voltage_domain) 19011630Sgabor.dozsa@arm.com 19111630Sgabor.dozsa@arm.com# Create a CPU voltage domain 19211630Sgabor.dozsa@arm.comsystem.cpu_voltage_domain = VoltageDomain() 19311569Sgabor.dozsa@arm.com 19411630Sgabor.dozsa@arm.com# Create a separate clock domain for the CPUs 19511569Sgabor.dozsa@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 19611630Sgabor.dozsa@arm.com voltage_domain = 19711630Sgabor.dozsa@arm.com system.cpu_voltage_domain) 19811569Sgabor.dozsa@arm.com 19911630Sgabor.dozsa@arm.com# All cpus belong to a common cpu_clk_domain, therefore running at a common 20011569Sgabor.dozsa@arm.com# frequency. 20111630Sgabor.dozsa@arm.comfor cpu in system.cpu: 20211630Sgabor.dozsa@arm.com cpu.clk_domain = system.cpu_clk_domain 20311630Sgabor.dozsa@arm.com 20411569Sgabor.dozsa@arm.comif is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass): 20511630Sgabor.dozsa@arm.com if buildEnv['TARGET_ISA'] == 'x86': 20611630Sgabor.dozsa@arm.com system.vm = KvmVM() 20711630Sgabor.dozsa@arm.com for process in multiprocesses: 20811630Sgabor.dozsa@arm.com process.useArchPT = True 20911756Sgabor.dozsa@arm.com process.kvmInSE = True 21013636Sgiacomo.travaglini@arm.com else: 21113636Sgiacomo.travaglini@arm.com fatal("KvmCPU can only be used in SE mode with x86") 21211756Sgabor.dozsa@arm.com 21311756Sgabor.dozsa@arm.com# Sanity check 21412148Sgabor.dozsa@arm.comif options.fastmem: 21511756Sgabor.dozsa@arm.com if CPUClass != AtomicSimpleCPU: 21611756Sgabor.dozsa@arm.com fatal("Fastmem can only be used with atomic CPU!") 21712148Sgabor.dozsa@arm.com if (options.caches or options.l2cache): 21811630Sgabor.dozsa@arm.com fatal("You cannot use fastmem in combination with caches!") 21911630Sgabor.dozsa@arm.com 22011630Sgabor.dozsa@arm.comif options.simpoint_profile: 22111630Sgabor.dozsa@arm.com if not options.fastmem: 22211569Sgabor.dozsa@arm.com # Atomic CPU checked with fastmem option already 22311569Sgabor.dozsa@arm.com fatal("SimPoint generation should be done with atomic cpu and fastmem") 22411569Sgabor.dozsa@arm.com if np > 1: 22511569Sgabor.dozsa@arm.com fatal("SimPoint generation not supported with more than one CPUs") 22611569Sgabor.dozsa@arm.com 22711569Sgabor.dozsa@arm.comfor i in xrange(np): 22811569Sgabor.dozsa@arm.com if options.smt: 22911569Sgabor.dozsa@arm.com system.cpu[i].workload = multiprocesses 23011569Sgabor.dozsa@arm.com elif len(multiprocesses) == 1: 23111569Sgabor.dozsa@arm.com system.cpu[i].workload = multiprocesses[0] 23211756Sgabor.dozsa@arm.com else: 23311756Sgabor.dozsa@arm.com system.cpu[i].workload = multiprocesses[i] 23411756Sgabor.dozsa@arm.com 23511756Sgabor.dozsa@arm.com if options.fastmem: 23611756Sgabor.dozsa@arm.com system.cpu[i].fastmem = True 23711756Sgabor.dozsa@arm.com 23811569Sgabor.dozsa@arm.com if options.simpoint_profile: 23911569Sgabor.dozsa@arm.com system.cpu[i].addSimPointProbe(options.simpoint_interval) 24011569Sgabor.dozsa@arm.com 24111569Sgabor.dozsa@arm.com if options.checker: 24211569Sgabor.dozsa@arm.com system.cpu[i].addCheckerCpu() 24311630Sgabor.dozsa@arm.com 24411630Sgabor.dozsa@arm.com system.cpu[i].createThreads() 24511630Sgabor.dozsa@arm.com 24611630Sgabor.dozsa@arm.comif options.ruby: 24711630Sgabor.dozsa@arm.com if options.cpu_type == "atomic" or options.cpu_type == "AtomicSimpleCPU": 24811630Sgabor.dozsa@arm.com print >> sys.stderr, "Ruby does not work with atomic cpu!!" 24911630Sgabor.dozsa@arm.com sys.exit(1) 25011630Sgabor.dozsa@arm.com 25111630Sgabor.dozsa@arm.com Ruby.create_system(options, False, system) 25211630Sgabor.dozsa@arm.com assert(options.num_cpus == len(system.ruby._cpu_ports)) 25311630Sgabor.dozsa@arm.com 25411630Sgabor.dozsa@arm.com system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 25511630Sgabor.dozsa@arm.com voltage_domain = system.voltage_domain) 25611630Sgabor.dozsa@arm.com for i in xrange(np): 25711630Sgabor.dozsa@arm.com ruby_port = system.ruby._cpu_ports[i] 25811630Sgabor.dozsa@arm.com 25911630Sgabor.dozsa@arm.com # Create the interrupt controller and connect its ports to Ruby 26011630Sgabor.dozsa@arm.com # Note that the interrupt controller is always present but only 26111630Sgabor.dozsa@arm.com # in x86 does it have message ports that need to be connected 26211630Sgabor.dozsa@arm.com system.cpu[i].createInterruptController() 26311630Sgabor.dozsa@arm.com 26411630Sgabor.dozsa@arm.com # Connect the cpu's cache ports to Ruby 26511630Sgabor.dozsa@arm.com system.cpu[i].icache_port = ruby_port.slave 26611630Sgabor.dozsa@arm.com system.cpu[i].dcache_port = ruby_port.slave 26711630Sgabor.dozsa@arm.com if buildEnv['TARGET_ISA'] == 'x86': 26811630Sgabor.dozsa@arm.com system.cpu[i].interrupts.pio = ruby_port.master 26911630Sgabor.dozsa@arm.com system.cpu[i].interrupts.int_master = ruby_port.slave 27011630Sgabor.dozsa@arm.com system.cpu[i].interrupts.int_slave = ruby_port.master 27111630Sgabor.dozsa@arm.com system.cpu[i].itb.walker.port = ruby_port.slave 27211630Sgabor.dozsa@arm.com system.cpu[i].dtb.walker.port = ruby_port.slave 27311630Sgabor.dozsa@arm.comelse: 27411630Sgabor.dozsa@arm.com MemClass = Simulation.setMemClass(options) 27511630Sgabor.dozsa@arm.com system.membus = SystemXBar() 27611630Sgabor.dozsa@arm.com system.system_port = system.membus.slave 27711630Sgabor.dozsa@arm.com CacheConfig.config_cache(options, system) 27811630Sgabor.dozsa@arm.com MemConfig.config_mem(options, system) 27911630Sgabor.dozsa@arm.com 28011630Sgabor.dozsa@arm.comroot = Root(full_system = False, system = system) 28111630Sgabor.dozsa@arm.comSimulation.run(options, root, system, FutureClass) 282