se.py revision 10803
19793Sakash.bagdia@arm.com# Copyright (c) 2012-2013 ARM Limited
28706Sandreas.hansson@arm.com# All rights reserved.
38706Sandreas.hansson@arm.com#
48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall
58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual
68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating
78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software
88706Sandreas.hansson@arm.com# licensed hereunder.  You may use the software subject to the license
98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated
108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software,
118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form.
128706Sandreas.hansson@arm.com#
135369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan
143005Sstever@eecs.umich.edu# All rights reserved.
153005Sstever@eecs.umich.edu#
163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution;
233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its
243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
253005Sstever@eecs.umich.edu# this software without specific prior written permission.
263005Sstever@eecs.umich.edu#
273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
383005Sstever@eecs.umich.edu#
393005Sstever@eecs.umich.edu# Authors: Steve Reinhardt
403005Sstever@eecs.umich.edu
412710SN/A# Simple test script
422710SN/A#
433005Sstever@eecs.umich.edu# "m5 test.py"
442889SN/A
456654Snate@binkert.orgimport optparse
466654Snate@binkert.orgimport sys
479907Snilay@cs.wisc.eduimport os
486654Snate@binkert.org
492667SN/Aimport m5
506654Snate@binkert.orgfrom m5.defines import buildEnv
516654Snate@binkert.orgfrom m5.objects import *
526654Snate@binkert.orgfrom m5.util import addToPath, fatal
535457Ssaidi@eecs.umich.edu
546654Snate@binkert.orgaddToPath('../common')
558169SLisa.Hsu@amd.comaddToPath('../ruby')
568169SLisa.Hsu@amd.com
578920Snilay@cs.wisc.eduimport Options
588169SLisa.Hsu@amd.comimport Ruby
593395Shsul@eecs.umich.eduimport Simulation
606981SLisa.Hsu@amd.comimport CacheConfig
619836Sandreas.hansson@arm.comimport MemConfig
623448Shsul@eecs.umich.edufrom Caches import *
635369Ssaidi@eecs.umich.edufrom cpu2000 import *
643394Shsul@eecs.umich.edu
6510555Salexandru.dutu@amd.com# Check if KVM support has been enabled, we might need to do VM
6610555Salexandru.dutu@amd.com# configuration if that's the case.
6710555Salexandru.dutu@amd.comhave_kvm_support = 'BaseKvmCPU' in globals()
6810555Salexandru.dutu@amd.comdef is_kvm_cpu(cpu_class):
6910555Salexandru.dutu@amd.com    return have_kvm_support and cpu_class != None and \
7010555Salexandru.dutu@amd.com        issubclass(cpu_class, BaseKvmCPU)
7110555Salexandru.dutu@amd.com
729197Snilay@cs.wisc.edudef get_processes(options):
739197Snilay@cs.wisc.edu    """Interprets provided options and returns a list of processes"""
749197Snilay@cs.wisc.edu
759197Snilay@cs.wisc.edu    multiprocesses = []
769197Snilay@cs.wisc.edu    inputs = []
779197Snilay@cs.wisc.edu    outputs = []
789197Snilay@cs.wisc.edu    errouts = []
799197Snilay@cs.wisc.edu    pargs = []
809197Snilay@cs.wisc.edu
819197Snilay@cs.wisc.edu    workloads = options.cmd.split(';')
829197Snilay@cs.wisc.edu    if options.input != "":
839197Snilay@cs.wisc.edu        inputs = options.input.split(';')
849197Snilay@cs.wisc.edu    if options.output != "":
859197Snilay@cs.wisc.edu        outputs = options.output.split(';')
869197Snilay@cs.wisc.edu    if options.errout != "":
879197Snilay@cs.wisc.edu        errouts = options.errout.split(';')
889197Snilay@cs.wisc.edu    if options.options != "":
899197Snilay@cs.wisc.edu        pargs = options.options.split(';')
909197Snilay@cs.wisc.edu
919197Snilay@cs.wisc.edu    idx = 0
929197Snilay@cs.wisc.edu    for wrkld in workloads:
939197Snilay@cs.wisc.edu        process = LiveProcess()
949197Snilay@cs.wisc.edu        process.executable = wrkld
959907Snilay@cs.wisc.edu        process.cwd = os.getcwd()
969197Snilay@cs.wisc.edu
9710803Sbrandon.potter@amd.com        if options.env:
9810803Sbrandon.potter@amd.com            with open(options.env, 'r') as f:
9910803Sbrandon.potter@amd.com                process.env = [line.rstrip() for line in f]
10010803Sbrandon.potter@amd.com
1019197Snilay@cs.wisc.edu        if len(pargs) > idx:
1029217Snilay@cs.wisc.edu            process.cmd = [wrkld] + pargs[idx].split()
1039197Snilay@cs.wisc.edu        else:
1049197Snilay@cs.wisc.edu            process.cmd = [wrkld]
1059197Snilay@cs.wisc.edu
1069197Snilay@cs.wisc.edu        if len(inputs) > idx:
1079197Snilay@cs.wisc.edu            process.input = inputs[idx]
1089197Snilay@cs.wisc.edu        if len(outputs) > idx:
1099197Snilay@cs.wisc.edu            process.output = outputs[idx]
1109197Snilay@cs.wisc.edu        if len(errouts) > idx:
1119197Snilay@cs.wisc.edu            process.errout = errouts[idx]
1129197Snilay@cs.wisc.edu
1139197Snilay@cs.wisc.edu        multiprocesses.append(process)
1149197Snilay@cs.wisc.edu        idx += 1
1159197Snilay@cs.wisc.edu
1169197Snilay@cs.wisc.edu    if options.smt:
11710650Sandreas.hansson@arm.com        assert(options.cpu_type == "detailed")
1189197Snilay@cs.wisc.edu        return multiprocesses, idx
1199197Snilay@cs.wisc.edu    else:
1209197Snilay@cs.wisc.edu        return multiprocesses, 1
1219197Snilay@cs.wisc.edu
1229197Snilay@cs.wisc.edu
1232957SN/Aparser = optparse.OptionParser()
1248920Snilay@cs.wisc.eduOptions.addCommonOptions(parser)
1258920Snilay@cs.wisc.eduOptions.addSEOptions(parser)
1262957SN/A
1278862Snilay@cs.wisc.eduif '--ruby' in sys.argv:
1288862Snilay@cs.wisc.edu    Ruby.define_options(parser)
1298467Snilay@cs.wisc.edu
1302957SN/A(options, args) = parser.parse_args()
1312957SN/A
1322957SN/Aif args:
1332957SN/A    print "Error: script doesn't take any positional arguments"
1342957SN/A    sys.exit(1)
1352957SN/A
1368167SLisa.Hsu@amd.commultiprocesses = []
1379197Snilay@cs.wisc.edunumThreads = 1
1388167SLisa.Hsu@amd.com
1395369Ssaidi@eecs.umich.eduif options.bench:
1408167SLisa.Hsu@amd.com    apps = options.bench.split("-")
1418167SLisa.Hsu@amd.com    if len(apps) != options.num_cpus:
1428167SLisa.Hsu@amd.com        print "number of benchmarks not equal to set num_cpus!"
1438167SLisa.Hsu@amd.com        sys.exit(1)
1448167SLisa.Hsu@amd.com
1458167SLisa.Hsu@amd.com    for app in apps:
1468167SLisa.Hsu@amd.com        try:
1478168SLisa.Hsu@amd.com            if buildEnv['TARGET_ISA'] == 'alpha':
14810037SARM gem5 Developers                exec("workload = %s('alpha', 'tru64', '%s')" % (
14910037SARM gem5 Developers                        app, options.spec_input))
15010037SARM gem5 Developers            elif buildEnv['TARGET_ISA'] == 'arm':
15110037SARM gem5 Developers                exec("workload = %s('arm_%s', 'linux', '%s')" % (
15210037SARM gem5 Developers                        app, options.arm_iset, options.spec_input))
1538168SLisa.Hsu@amd.com            else:
15410037SARM gem5 Developers                exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')" % (
15510037SARM gem5 Developers                        app, options.spec_input))
1568167SLisa.Hsu@amd.com            multiprocesses.append(workload.makeLiveProcess())
1578167SLisa.Hsu@amd.com        except:
15810118Snilay@cs.wisc.edu            print >>sys.stderr, "Unable to find workload for %s: %s" % (
15910118Snilay@cs.wisc.edu                    buildEnv['TARGET_ISA'], app)
1605369Ssaidi@eecs.umich.edu            sys.exit(1)
1618920Snilay@cs.wisc.eduelif options.cmd:
1629197Snilay@cs.wisc.edu    multiprocesses, numThreads = get_processes(options)
1638920Snilay@cs.wisc.eduelse:
1648920Snilay@cs.wisc.edu    print >> sys.stderr, "No workload specified. Exiting!\n"
1658920Snilay@cs.wisc.edu    sys.exit(1)
1665369Ssaidi@eecs.umich.edu
1675369Ssaidi@eecs.umich.edu
1688718Snilay@cs.wisc.edu(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
1699197Snilay@cs.wisc.eduCPUClass.numThreads = numThreads
1709197Snilay@cs.wisc.edu
1719197Snilay@cs.wisc.edu# Check -- do not allow SMT with multiple CPUs
1729197Snilay@cs.wisc.eduif options.smt and options.num_cpus > 1:
1739197Snilay@cs.wisc.edu    fatal("You cannot use SMT with multiple CPUs!")
1743005Sstever@eecs.umich.edu
1753395Shsul@eecs.umich.edunp = options.num_cpus
1763395Shsul@eecs.umich.edusystem = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
1779793Sakash.bagdia@arm.com                mem_mode = test_mem_mode,
1789836Sandreas.hansson@arm.com                mem_ranges = [AddrRange(options.mem_size)],
1799815SAndreas Hansson <andreas.hansson>                cache_line_size = options.cacheline_size)
1809793Sakash.bagdia@arm.com
1819827Sakash.bagdia@arm.com# Create a top-level voltage domain
1829827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
1839827Sakash.bagdia@arm.com
1849827Sakash.bagdia@arm.com# Create a source clock for the system and set the clock period
1859827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock =  options.sys_clock,
1869827Sakash.bagdia@arm.com                                   voltage_domain = system.voltage_domain)
1879827Sakash.bagdia@arm.com
1889827Sakash.bagdia@arm.com# Create a CPU voltage domain
1899827Sakash.bagdia@arm.comsystem.cpu_voltage_domain = VoltageDomain()
1909827Sakash.bagdia@arm.com
1919793Sakash.bagdia@arm.com# Create a separate clock domain for the CPUs
1929827Sakash.bagdia@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
1939827Sakash.bagdia@arm.com                                       voltage_domain =
1949827Sakash.bagdia@arm.com                                       system.cpu_voltage_domain)
1959793Sakash.bagdia@arm.com
1969793Sakash.bagdia@arm.com# All cpus belong to a common cpu_clk_domain, therefore running at a common
1979793Sakash.bagdia@arm.com# frequency.
1989793Sakash.bagdia@arm.comfor cpu in system.cpu:
1999793Sakash.bagdia@arm.com    cpu.clk_domain = system.cpu_clk_domain
2003395Shsul@eecs.umich.edu
20110555Salexandru.dutu@amd.comif is_kvm_cpu(CPUClass) or is_kvm_cpu(FutureClass):
20210555Salexandru.dutu@amd.com    if buildEnv['TARGET_ISA'] == 'x86':
20310555Salexandru.dutu@amd.com        system.vm = KvmVM()
20410555Salexandru.dutu@amd.com        for process in multiprocesses:
20510555Salexandru.dutu@amd.com            process.useArchPT = True
20610555Salexandru.dutu@amd.com            process.kvmInSE = True
20710555Salexandru.dutu@amd.com    else:
20810555Salexandru.dutu@amd.com        fatal("KvmCPU can only be used in SE mode with x86")
20910555Salexandru.dutu@amd.com
2108926Sandreas.hansson@arm.com# Sanity check
2119317Sandreas.hansson@arm.comif options.fastmem:
2129317Sandreas.hansson@arm.com    if CPUClass != AtomicSimpleCPU:
2139317Sandreas.hansson@arm.com        fatal("Fastmem can only be used with atomic CPU!")
2149317Sandreas.hansson@arm.com    if (options.caches or options.l2cache):
2159317Sandreas.hansson@arm.com        fatal("You cannot use fastmem in combination with caches!")
2168926Sandreas.hansson@arm.com
2179647Sdam.sunwoo@arm.comif options.simpoint_profile:
2189647Sdam.sunwoo@arm.com    if not options.fastmem:
2199647Sdam.sunwoo@arm.com        # Atomic CPU checked with fastmem option already
2209647Sdam.sunwoo@arm.com        fatal("SimPoint generation should be done with atomic cpu and fastmem")
2219647Sdam.sunwoo@arm.com    if np > 1:
2229647Sdam.sunwoo@arm.com        fatal("SimPoint generation not supported with more than one CPUs")
2239647Sdam.sunwoo@arm.com
2243395Shsul@eecs.umich.edufor i in xrange(np):
2259197Snilay@cs.wisc.edu    if options.smt:
2269197Snilay@cs.wisc.edu        system.cpu[i].workload = multiprocesses
2279197Snilay@cs.wisc.edu    elif len(multiprocesses) == 1:
2288957Sjayneel@cs.wisc.edu        system.cpu[i].workload = multiprocesses[0]
2298957Sjayneel@cs.wisc.edu    else:
2308957Sjayneel@cs.wisc.edu        system.cpu[i].workload = multiprocesses[i]
2313005Sstever@eecs.umich.edu
2324968Sacolyte@umich.edu    if options.fastmem:
2339006Sandreas.hansson@arm.com        system.cpu[i].fastmem = True
2344968Sacolyte@umich.edu
2359647Sdam.sunwoo@arm.com    if options.simpoint_profile:
23610381Sdam.sunwoo@arm.com        system.cpu[i].addSimPointProbe(options.simpoint_interval)
2379647Sdam.sunwoo@arm.com
2388887Sgeoffrey.blake@arm.com    if options.checker:
2398887Sgeoffrey.blake@arm.com        system.cpu[i].addCheckerCpu()
2408887Sgeoffrey.blake@arm.com
2419384SAndreas.Sandberg@arm.com    system.cpu[i].createThreads()
2429384SAndreas.Sandberg@arm.com
2438887Sgeoffrey.blake@arm.comif options.ruby:
2448896Snilay@cs.wisc.edu    if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
2458896Snilay@cs.wisc.edu        print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
2468896Snilay@cs.wisc.edu        sys.exit(1)
2478896Snilay@cs.wisc.edu
24810519Snilay@cs.wisc.edu    Ruby.create_system(options, False, system)
24910120Snilay@cs.wisc.edu    assert(options.num_cpus == len(system.ruby._cpu_ports))
2508896Snilay@cs.wisc.edu
25110300Scastilloe@unican.es    system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
25210300Scastilloe@unican.es                                        voltage_domain = system.voltage_domain)
2538896Snilay@cs.wisc.edu    for i in xrange(np):
25410120Snilay@cs.wisc.edu        ruby_port = system.ruby._cpu_ports[i]
2558896Snilay@cs.wisc.edu
2568896Snilay@cs.wisc.edu        # Create the interrupt controller and connect its ports to Ruby
2579268Smalek.musleh@gmail.com        # Note that the interrupt controller is always present but only
2589268Smalek.musleh@gmail.com        # in x86 does it have message ports that need to be connected
2598896Snilay@cs.wisc.edu        system.cpu[i].createInterruptController()
2608896Snilay@cs.wisc.edu
2618896Snilay@cs.wisc.edu        # Connect the cpu's cache ports to Ruby
2628896Snilay@cs.wisc.edu        system.cpu[i].icache_port = ruby_port.slave
2638896Snilay@cs.wisc.edu        system.cpu[i].dcache_port = ruby_port.slave
2649222Shestness@cs.wisc.edu        if buildEnv['TARGET_ISA'] == 'x86':
2659268Smalek.musleh@gmail.com            system.cpu[i].interrupts.pio = ruby_port.master
2669268Smalek.musleh@gmail.com            system.cpu[i].interrupts.int_master = ruby_port.slave
2679268Smalek.musleh@gmail.com            system.cpu[i].interrupts.int_slave = ruby_port.master
2689222Shestness@cs.wisc.edu            system.cpu[i].itb.walker.port = ruby_port.slave
2699222Shestness@cs.wisc.edu            system.cpu[i].dtb.walker.port = ruby_port.slave
2708887Sgeoffrey.blake@arm.comelse:
27110150Snilay@cs.wisc.edu    MemClass = Simulation.setMemClass(options)
27210720Sandreas.hansson@arm.com    system.membus = SystemXBar()
2738887Sgeoffrey.blake@arm.com    system.system_port = system.membus.slave
2748887Sgeoffrey.blake@arm.com    CacheConfig.config_cache(options, system)
2759836Sandreas.hansson@arm.com    MemConfig.config_mem(options, system)
2768887Sgeoffrey.blake@arm.com
2778801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system)
2783481Shsul@eecs.umich.eduSimulation.run(options, root, system, FutureClass)
279