ruby_random_test.py revision 10120
16019Shines@cs.fsu.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 211495Sandreas.sandberg@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 37093Sgblack@eecs.umich.edu# All rights reserved. 47093Sgblack@eecs.umich.edu# 57093Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 67093Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 77093Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 87093Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 97093Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 107093Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 117093Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 127093Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 137093Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu# this software without specific prior written permission. 156019Shines@cs.fsu.edu# 166019Shines@cs.fsu.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu# 286019Shines@cs.fsu.edu# Authors: Ron Dreslinski 296019Shines@cs.fsu.edu# Brad Beckmann 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.eduimport m5 326019Shines@cs.fsu.edufrom m5.objects import * 336019Shines@cs.fsu.edufrom m5.defines import buildEnv 346019Shines@cs.fsu.edufrom m5.util import addToPath 356019Shines@cs.fsu.eduimport os, optparse, sys 366019Shines@cs.fsu.eduaddToPath('../common') 376019Shines@cs.fsu.eduaddToPath('../ruby') 386019Shines@cs.fsu.eduaddToPath('../topologies') 396019Shines@cs.fsu.edu 407399SAli.Saidi@ARM.comimport Options 417399SAli.Saidi@ARM.comimport Ruby 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu# Get paths we might need. It's expected this file is in m5/configs/example. 446019Shines@cs.fsu.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 4510873Sandreas.sandberg@arm.comconfig_root = os.path.dirname(config_path) 4610873Sandreas.sandberg@arm.comm5_root = os.path.dirname(config_root) 4710474Sandreas.hansson@arm.com 486019Shines@cs.fsu.eduparser = optparse.OptionParser() 496019Shines@cs.fsu.eduOptions.addCommonOptions(parser) 506019Shines@cs.fsu.edu 516116Snate@binkert.orgparser.add_option("--maxloads", metavar="N", default=100, 526019Shines@cs.fsu.edu help="Stop after N loads") 538782Sgblack@eecs.umich.eduparser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 548756Sgblack@eecs.umich.edu help="Wakeup every N cycles") 5510037SARM gem5 Developers 5610037SARM gem5 Developers# 576019Shines@cs.fsu.edu# Add the ruby specific and protocol specific options 586019Shines@cs.fsu.edu# 596019Shines@cs.fsu.eduRuby.define_options(parser) 606019Shines@cs.fsu.edu 6110024Sdam.sunwoo@arm.comexecfile(os.path.join(config_root, "common", "Options.py")) 626019Shines@cs.fsu.edu 638232Snate@binkert.org(options, args) = parser.parse_args() 648232Snate@binkert.org 658232Snate@binkert.org# 666116Snate@binkert.org# Set the default cache size and associativity to be very small to encourage 6711608Snikos.nikoleris@arm.com# races between requests and writebacks. 686116Snate@binkert.org# 698756Sgblack@eecs.umich.eduoptions.l1d_size="256B" 706019Shines@cs.fsu.eduoptions.l1i_size="256B" 716019Shines@cs.fsu.eduoptions.l2_size="512B" 726019Shines@cs.fsu.eduoptions.l3_size="1kB" 736019Shines@cs.fsu.eduoptions.l1d_assoc=2 746019Shines@cs.fsu.eduoptions.l1i_assoc=2 7510037SARM gem5 Developersoptions.l2_assoc=2 7610037SARM gem5 Developersoptions.l3_assoc=2 7710418Sandreas.hansson@arm.com 7810418Sandreas.hansson@arm.comif args: 7911395Sandreas.sandberg@arm.com print "Error: script doesn't take any positional arguments" 8010537Sandreas.hansson@arm.com sys.exit(1) 8110537Sandreas.hansson@arm.com 8211152Smitch.hayenga@arm.com# 836019Shines@cs.fsu.edu# Create the ruby random tester 8410037SARM gem5 Developers# 857399SAli.Saidi@ARM.com 8610037SARM gem5 Developers# Check the protocol 8710037SARM gem5 Developerscheck_flush = False 8810037SARM gem5 Developersif buildEnv['PROTOCOL'] == 'MOESI_hammer': 8910037SARM gem5 Developers check_flush = True 906019Shines@cs.fsu.edu 916019Shines@cs.fsu.edutester = RubyTester(check_flush = check_flush, 926019Shines@cs.fsu.edu checks_to_complete = options.maxloads, 936019Shines@cs.fsu.edu wakeup_frequency = options.wakeup_freq) 9410037SARM gem5 Developers 9510037SARM gem5 Developers# 9610037SARM gem5 Developers# Create the M5 system. Note that the Memory Object isn't 9710037SARM gem5 Developers# actually used by the rubytester, but is included to support the 9810037SARM gem5 Developers# M5 memory size == Ruby memory size checks 9910037SARM gem5 Developers# 10010037SARM gem5 Developerssystem = System(tester = tester, physmem = SimpleMemory(), 10110037SARM gem5 Developers mem_ranges = [AddrRange(options.mem_size)]) 10210037SARM gem5 Developers 10310037SARM gem5 Developers# Create a top-level voltage domain and clock domain 10410037SARM gem5 Developerssystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 10510717Sandreas.hansson@arm.com 10610037SARM gem5 Developerssystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 10710037SARM gem5 Developers voltage_domain = system.voltage_domain) 10810717Sandreas.hansson@arm.com 1096019Shines@cs.fsu.eduRuby.create_system(options, system) 1106019Shines@cs.fsu.edu 1117694SAli.Saidi@ARM.com# Create a seperate clock domain for Ruby 1127694SAli.Saidi@ARM.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1137694SAli.Saidi@ARM.com voltage_domain = system.voltage_domain) 11410037SARM gem5 Developers 11510037SARM gem5 Developersassert(options.num_cpus == len(system.ruby._cpu_ports)) 11610037SARM gem5 Developers 11710037SARM gem5 Developerstester.num_cpus = len(system.ruby._cpu_ports) 11810037SARM gem5 Developers 11910037SARM gem5 Developers# 12010037SARM gem5 Developers# The tester is most effective when randomization is turned on and 12110037SARM gem5 Developers# artifical delay is randomly inserted on messages 12210037SARM gem5 Developers# 1237694SAli.Saidi@ARM.comsystem.ruby.randomization = True 1247694SAli.Saidi@ARM.com 1257694SAli.Saidi@ARM.comfor ruby_port in system.ruby._cpu_ports: 1267694SAli.Saidi@ARM.com # 1277694SAli.Saidi@ARM.com # Tie the ruby tester ports to the ruby cpu read and write ports 1287694SAli.Saidi@ARM.com # 1299738Sandreas@sandberg.pp.se if ruby_port.support_data_reqs: 1309738Sandreas@sandberg.pp.se tester.cpuDataPort = ruby_port.slave 1319738Sandreas@sandberg.pp.se if ruby_port.support_inst_reqs: 1329738Sandreas@sandberg.pp.se tester.cpuInstPort = ruby_port.slave 1339738Sandreas@sandberg.pp.se 1349738Sandreas@sandberg.pp.se # 1357404SAli.Saidi@ARM.com # Tell each sequencer this is the ruby tester so that it 13610037SARM gem5 Developers # copies the subblock back to the checker 13710037SARM gem5 Developers # 1386019Shines@cs.fsu.edu ruby_port.using_ruby_tester = True 1397404SAli.Saidi@ARM.com 1407404SAli.Saidi@ARM.com # 1417404SAli.Saidi@ARM.com # Ruby doesn't need the backing image of memory when running with 14210037SARM gem5 Developers # the tester. 1437404SAli.Saidi@ARM.com # 1447404SAli.Saidi@ARM.com ruby_port.access_phys_mem = False 14510037SARM gem5 Developers 14610037SARM gem5 Developers# ----------------------- 14710037SARM gem5 Developers# run simulation 14810037SARM gem5 Developers# ----------------------- 14910037SARM gem5 Developers 1509535Smrinmoy.ghosh@arm.comroot = Root( full_system = False, system = system ) 1517697SAli.Saidi@ARM.comroot.system.mem_mode = 'timing' 15211321Ssteve.reinhardt@amd.com 15310037SARM gem5 Developers# Not much point in this being higher than the L1 latency 1547697SAli.Saidi@ARM.comm5.ticks.setGlobalFrequency('1ns') 1557697SAli.Saidi@ARM.com 1567697SAli.Saidi@ARM.com# instantiate configuration 1577697SAli.Saidi@ARM.comm5.instantiate() 1587697SAli.Saidi@ARM.com 1597404SAli.Saidi@ARM.com# simulate until program terminates 1607404SAli.Saidi@ARM.comexit_event = m5.simulate(options.abs_max_tick) 16110037SARM gem5 Developers 1627404SAli.Saidi@ARM.comprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 1637404SAli.Saidi@ARM.com