ruby_gpu_random_test.py revision 11682
14202Sbinkertn@umich.edu# 24202Sbinkertn@umich.edu# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. 34202Sbinkertn@umich.edu# All rights reserved. 44202Sbinkertn@umich.edu# 54202Sbinkertn@umich.edu# For use for simulation and test purposes only 64202Sbinkertn@umich.edu# 74202Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 84202Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are met: 94202Sbinkertn@umich.edu# 104202Sbinkertn@umich.edu# 1. Redistributions of source code must retain the above copyright notice, 114202Sbinkertn@umich.edu# this list of conditions and the following disclaimer. 124202Sbinkertn@umich.edu# 134202Sbinkertn@umich.edu# 2. Redistributions in binary form must reproduce the above copyright notice, 144202Sbinkertn@umich.edu# this list of conditions and the following disclaimer in the documentation 154202Sbinkertn@umich.edu# and/or other materials provided with the distribution. 164202Sbinkertn@umich.edu# 174202Sbinkertn@umich.edu# 3. Neither the name of the copyright holder nor the names of its contributors 184202Sbinkertn@umich.edu# may be used to endorse or promote products derived from this software 194202Sbinkertn@umich.edu# without specific prior written permission. 204202Sbinkertn@umich.edu# 214202Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 224202Sbinkertn@umich.edu# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 234202Sbinkertn@umich.edu# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 244202Sbinkertn@umich.edu# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 254202Sbinkertn@umich.edu# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 264202Sbinkertn@umich.edu# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 274202Sbinkertn@umich.edu# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 284202Sbinkertn@umich.edu# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 294202Sbinkertn@umich.edu# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 304202Sbinkertn@umich.edu# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 314202Sbinkertn@umich.edu# POSSIBILITY OF SUCH DAMAGE. 324202Sbinkertn@umich.edu# 339157Sandreas.hansson@arm.com# Author: Brad Beckmann 3410259SAndrew.Bardsley@arm.com# 354486Sbinkertn@umich.edu 369793Sakash.bagdia@arm.comimport m5 379827Sakash.bagdia@arm.comfrom m5.objects import * 389850Sandreas.hansson@arm.comfrom m5.defines import buildEnv 3910249Sstephan.diestelhorst@arm.comfrom m5.util import addToPath 4010268SGeoffrey.Blake@arm.comimport os, optparse, sys 414486Sbinkertn@umich.edu 428774Sgblack@eecs.umich.eduaddToPath('../') 434202Sbinkertn@umich.edu 4411235Sandreas.sandberg@arm.comfrom common import Options 454202Sbinkertn@umich.edufrom ruby import Ruby 4611077SCurtis.Dunham@arm.com 4710458Sandreas.hansson@arm.com# Get paths we might need. 4810458Sandreas.hansson@arm.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 4910458Sandreas.hansson@arm.comconfig_root = os.path.dirname(config_path) 504202Sbinkertn@umich.edum5_root = os.path.dirname(config_root) 5110453SAndrew.Bardsley@arm.com 524202Sbinkertn@umich.eduparser = optparse.OptionParser() 539983Sstever@gmail.comOptions.addCommonOptions(parser) 5410453SAndrew.Bardsley@arm.com 5510453SAndrew.Bardsley@arm.comparser.add_option("--maxloads", metavar="N", default=100, 568233Snate@binkert.org help="Stop after N loads") 574202Sbinkertn@umich.eduparser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 584202Sbinkertn@umich.edu help="Wakeup every N cycles") 599342SAndreas.Sandberg@arm.comparser.add_option("-u", "--num-compute-units", type="int", default=1, 604202Sbinkertn@umich.edu help="number of compute units in the GPU") 614202Sbinkertn@umich.eduparser.add_option("--num-cp", type="int", default=0, 6210268SGeoffrey.Blake@arm.com help="Number of GPU Command Processors (CP)") 6310259SAndrew.Bardsley@arm.com# not super important now, but to avoid putting the number 4 everywhere, make 644202Sbinkertn@umich.edu# it an option/knob 654202Sbinkertn@umich.eduparser.add_option("--cu-per-sqc", type="int", default=4, help="number of CUs \ 6610453SAndrew.Bardsley@arm.com sharing an SQC (icache, and thus icache TLB)") 679793Sakash.bagdia@arm.comparser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \ 689827Sakash.bagdia@arm.com "per CU") 6911420Sdavid.guillen@arm.comparser.add_option("--wf-size", type="int", default=64, 709850Sandreas.hansson@arm.com help="Wavefront size(in workitems)") 7110249Sstephan.diestelhorst@arm.comparser.add_option("--wfs-per-simd", type="int", default=10, help="Number of " \ 7211524Sdavid.guillen@arm.com "WF slots per SIMD") 7311527Sdavid.guillen@arm.com 747768SAli.Saidi@ARM.com# 759850Sandreas.hansson@arm.com# Add the ruby specific and protocol specific options 769850Sandreas.hansson@arm.com# 778766Sgblack@eecs.umich.eduRuby.define_options(parser) 7811854Sbrandon.potter@amd.com 797768SAli.Saidi@ARM.comexecfile(os.path.join(config_root, "common", "Options.py")) 808766Sgblack@eecs.umich.edu 8111856Sbrandon.potter@amd.com(options, args) = parser.parse_args() 8210930Sbrandon.potter@amd.com 837768SAli.Saidi@ARM.com# 849850Sandreas.hansson@arm.com# Set the default cache size and associativity to be very small to encourage 8511794Sbrandon.potter@amd.com# races between requests and writebacks. 864486Sbinkertn@umich.edu# 8711800Sbrandon.potter@amd.comoptions.l1d_size="256B" 8811800Sbrandon.potter@amd.comoptions.l1i_size="256B" 8911800Sbrandon.potter@amd.comoptions.l2_size="512B" 908335Snate@binkert.orgoptions.l3_size="1kB" 918335Snate@binkert.orgoptions.l1d_assoc=2 9210458Sandreas.hansson@arm.comoptions.l1i_assoc=2 939152Satgutier@umich.eduoptions.l2_assoc=2 948335Snate@binkert.orgoptions.l3_assoc=2 958335Snate@binkert.org 968335Snate@binkert.org# This file can support multiple compute units 978335Snate@binkert.orgassert(options.num_compute_units >= 1) 988335Snate@binkert.orgn_cu = options.num_compute_units 998335Snate@binkert.org 1008335Snate@binkert.orgoptions.num_sqc = int((n_cu + options.cu_per_sqc - 1) / options.cu_per_sqc) 1019733Sandreas@sandberg.pp.se 1028335Snate@binkert.orgif args: 10311380Salexandru.dutu@amd.com print "Error: script doesn't take any positional arguments" 1048335Snate@binkert.org sys.exit(1) 1058335Snate@binkert.org 1068335Snate@binkert.org# 1078335Snate@binkert.org# Create the ruby random tester 1088335Snate@binkert.org# 1098335Snate@binkert.org 1109793Sakash.bagdia@arm.com# Check to for the GPU_RfO protocol. Other GPU protocols are non-SC and will 1119827Sakash.bagdia@arm.com# not work with the Ruby random tester. 11210249Sstephan.diestelhorst@arm.comassert(buildEnv['PROTOCOL'] == 'GPU_RfO') 11311380Salexandru.dutu@amd.com 11411380Salexandru.dutu@amd.com# The GPU_RfO protocol does not support cache flushes 115check_flush = False 116 117tester = RubyTester(check_flush=check_flush, 118 checks_to_complete=options.maxloads, 119 wakeup_frequency=options.wakeup_freq, 120 deadlock_threshold=1000000) 121 122# 123# Create the M5 system. Note that the Memory Object isn't 124# actually used by the rubytester, but is included to support the 125# M5 memory size == Ruby memory size checks 126# 127system = System(cpu=tester, mem_ranges=[AddrRange(options.mem_size)]) 128 129# Create a top-level voltage domain and clock domain 130system.voltage_domain = VoltageDomain(voltage=options.sys_voltage) 131 132system.clk_domain = SrcClockDomain(clock=options.sys_clock, 133 voltage_domain=system.voltage_domain) 134 135Ruby.create_system(options, False, system) 136 137# Create a seperate clock domain for Ruby 138system.ruby.clk_domain = SrcClockDomain(clock=options.ruby_clock, 139 voltage_domain=system.voltage_domain) 140 141tester.num_cpus = len(system.ruby._cpu_ports) 142 143# 144# The tester is most effective when randomization is turned on and 145# artifical delay is randomly inserted on messages 146# 147system.ruby.randomization = True 148 149for ruby_port in system.ruby._cpu_ports: 150 151 # 152 # Tie the ruby tester ports to the ruby cpu read and write ports 153 # 154 if ruby_port.support_data_reqs and ruby_port.support_inst_reqs: 155 tester.cpuInstDataPort = ruby_port.slave 156 elif ruby_port.support_data_reqs: 157 tester.cpuDataPort = ruby_port.slave 158 elif ruby_port.support_inst_reqs: 159 tester.cpuInstPort = ruby_port.slave 160 161 # Do not automatically retry stalled Ruby requests 162 ruby_port.no_retry_on_stall = True 163 164 # 165 # Tell each sequencer this is the ruby tester so that it 166 # copies the subblock back to the checker 167 # 168 ruby_port.using_ruby_tester = True 169 170# ----------------------- 171# run simulation 172# ----------------------- 173 174root = Root( full_system = False, system = system ) 175root.system.mem_mode = 'timing' 176 177# Not much point in this being higher than the L1 latency 178m5.ticks.setGlobalFrequency('1ns') 179 180# instantiate configuration 181m5.instantiate() 182 183# simulate until program terminates 184exit_event = m5.simulate(options.abs_max_tick) 185 186print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 187