memtest.py revision 4891 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31import os, optparse, sys
32m5.AddToPath('../common')
33
34parser = optparse.OptionParser()
35
36parser.add_option("-c", "--cache-levels", type="int", default=2,
37                  metavar="LEVELS",
38                  help="Number of cache levels [default: %default]")
39parser.add_option("-a", "--atomic", action="store_true",
40                  help="Use atomic (non-timing) mode")
41parser.add_option("-b", "--blocking", action="store_true",
42                  help="Use blocking caches")
43parser.add_option("-l", "--maxloads", default="1G", metavar="N",
44                  help="Stop after N loads [default: %default]")
45parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
46                  metavar="T",
47                  help="Stop after T ticks")
48parser.add_option("-n", "--numtesters", type="int", default=8,
49                  metavar="N",
50                  help="Number of tester pseudo-CPUs [default: %default]")
51
52parser.add_option("-t", "--treespec", type="string",
53                  help="Colon-separated multilevel tree specification")
54
55parser.add_option("--force-bus", action="store_true",
56                  help="Use bus between levels even with single cache")
57
58parser.add_option("-f", "--functional", type="int", default=0,
59                  metavar="PCT",
60                  help="Target percentage of functional accesses "
61                  "[default: %default]")
62parser.add_option("-u", "--uncacheable", type="int", default=0,
63                  metavar="PCT",
64                  help="Target percentage of uncacheable accesses "
65                  "[default: %default]")
66
67parser.add_option("--progress", type="int", default=1000,
68                  metavar="NLOADS",
69                  help="Progress message interval "
70                  "[default: %default]")
71
72(options, args) = parser.parse_args()
73
74if args:
75     print "Error: script doesn't take any positional arguments"
76     sys.exit(1)
77
78block_size = 64
79
80if not options.treespec:
81     # convert simple cache_levels option to treespec
82     treespec = [options.numtesters, 1]
83     numtesters = options.numtesters
84else:
85     try:
86          treespec = [int(x) for x in options.treespec.split(':')]
87          numtesters = reduce(lambda x,y: x*y, treespec)
88     except:
89          print "Error parsing treespec option"
90          sys.exit(1)
91
92if numtesters > block_size:
93     print "Error: Number of testers limited to %s because of false sharing" \
94           % (block_size)
95     sys.exit(1)
96
97if len(treespec) < 1:
98     print "Error parsing treespec"
99     sys.exit(1)
100
101# define prototype L1 cache
102proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
103                     latency = '1ns', tgts_per_mshr = 8)
104
105if options.blocking:
106     proto_l1.mshrs = 1
107else:
108     proto_l1.mshrs = 8
109
110# build a list of prototypes, one for each cache level (L1 is at end,
111# followed by the tester pseudo-cpu objects)
112prototypes = [ proto_l1,
113               MemTest(atomic=options.atomic, max_loads=options.maxloads,
114                       percent_functional=options.functional,
115                       percent_uncacheable=options.uncacheable,
116                       progress_interval=options.progress) ]
117
118while len(prototypes) < len(treespec):
119     # clone previous level and update params
120     prev = prototypes[0]
121     next = prev()
122     next.size = prev.size * 4
123     next.latency = prev.latency * 10
124     next.assoc = prev.assoc * 2
125     prototypes.insert(0, next)
126
127# system simulated
128system = System(funcmem = PhysicalMemory(),
129                physmem = PhysicalMemory(latency = "100ns"))
130
131def make_level(spec, prototypes, attach_obj, attach_port):
132     fanout = spec[0]
133     parent = attach_obj # use attach obj as config parent too
134     if fanout > 1 or options.force_bus:
135          new_bus = Bus(clock="500MHz", width=16)
136          new_bus.port = getattr(attach_obj, attach_port)
137          parent.cpu_side_bus = new_bus
138          attach_obj = new_bus
139          attach_port = "port"
140     objs = [prototypes[0]() for i in xrange(fanout)]
141     if len(spec) > 1:
142          # we just built caches, more levels to go
143          parent.cache = objs
144          for cache in objs:
145               cache.mem_side = getattr(attach_obj, attach_port)
146               make_level(spec[1:], prototypes[1:], cache, "cpu_side")
147     else:
148          # we just built the MemTest objects
149          parent.cpu = objs
150          for t in objs:
151               t.test = getattr(attach_obj, attach_port)
152               t.functional = system.funcmem.port
153
154make_level(treespec, prototypes, system.physmem, "port")
155
156# -----------------------
157# run simulation
158# -----------------------
159
160root = Root( system = system )
161if options.atomic:
162    root.system.mem_mode = 'atomic'
163else:
164    root.system.mem_mode = 'timing'
165
166# Not much point in this being higher than the L1 latency
167m5.ticks.setGlobalFrequency('1ns')
168
169# instantiate configuration
170m5.instantiate(root)
171
172# simulate until program terminates
173exit_event = m5.simulate(options.maxtick)
174
175print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
176