memtest.py revision 4890 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31import os, optparse, sys
32m5.AddToPath('../common')
33
34parser = optparse.OptionParser()
35
36parser.add_option("-c", "--cache-levels", type="int", default=2,
37                  metavar="LEVELS",
38                  help="Number of cache levels [default: %default]")
39parser.add_option("-a", "--atomic", action="store_true",
40                  help="Use atomic (non-timing) mode")
41parser.add_option("-b", "--blocking", action="store_true",
42                  help="Use blocking caches")
43parser.add_option("-l", "--maxloads", default="1G", metavar="N",
44                  help="Stop after N loads [default: %default]")
45parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
46                  metavar="T",
47                  help="Stop after T ticks")
48parser.add_option("-n", "--numtesters", type="int", default=8,
49                  metavar="N",
50                  help="Number of tester pseudo-CPUs [default: %default]")
51
52parser.add_option("-t", "--treespec", type="string",
53                  help="Colon-separated multilevel tree specification")
54
55
56parser.add_option("-f", "--functional", type="int", default=0,
57                  metavar="PCT",
58                  help="Target percentage of functional accesses "
59                  "[default: %default]")
60parser.add_option("-u", "--uncacheable", type="int", default=0,
61                  metavar="PCT",
62                  help="Target percentage of uncacheable accesses "
63                  "[default: %default]")
64
65parser.add_option("--progress", type="int", default=1000,
66                  metavar="NLOADS",
67                  help="Progress message interval "
68                  "[default: %default]")
69
70(options, args) = parser.parse_args()
71
72if args:
73     print "Error: script doesn't take any positional arguments"
74     sys.exit(1)
75
76block_size = 64
77
78if not options.treespec:
79     # convert simple cache_levels option to treespec
80     treespec = [options.numtesters, 1]
81     numtesters = options.numtesters
82else:
83     try:
84          treespec = [int(x) for x in options.treespec.split(':')]
85          numtesters = reduce(lambda x,y: x*y, treespec)
86     except:
87          print "Error parsing treespec option"
88          sys.exit(1)
89
90if numtesters > block_size:
91     print "Error: Number of testers limited to %s because of false sharing" \
92           % (block_size)
93     sys.exit(1)
94
95if len(treespec) < 1:
96     print "Error parsing treespec"
97     sys.exit(1)
98
99# define prototype L1 cache
100proto_l1 = BaseCache(size = '32kB', assoc = 4, block_size = block_size,
101                     latency = '1ns', tgts_per_mshr = 8)
102
103if options.blocking:
104     proto_l1.mshrs = 1
105else:
106     proto_l1.mshrs = 8
107
108# build a list of prototypes, one for each cache level (L1 is at end,
109# followed by the tester pseudo-cpu objects)
110prototypes = [ proto_l1,
111               MemTest(atomic=options.atomic, max_loads=options.maxloads,
112                       percent_functional=options.functional,
113                       percent_uncacheable=options.uncacheable,
114                       progress_interval=options.progress) ]
115
116while len(prototypes) < len(treespec):
117     # clone previous level and update params
118     prev = prototypes[0]
119     next = prev()
120     next.size = prev.size * 4
121     next.latency = prev.latency * 10
122     next.assoc = prev.assoc * 2
123     prototypes.insert(0, next)
124
125# system simulated
126system = System(funcmem = PhysicalMemory(),
127                physmem = PhysicalMemory(latency = "100ns"))
128
129def make_level(spec, prototypes, attach_obj, attach_port):
130     fanout = spec[0]
131     parent = attach_obj # use attach obj as config parent too
132     if fanout > 1:
133          new_bus = Bus(clock="500MHz", width=16)
134          new_bus.port = getattr(attach_obj, attach_port)
135          parent.cpu_side_bus = new_bus
136          attach_obj = new_bus
137          attach_port = "port"
138     objs = [prototypes[0]() for i in xrange(fanout)]
139     if len(spec) > 1:
140          # we just built caches, more levels to go
141          parent.cache = objs
142          for cache in objs:
143               cache.mem_side = getattr(attach_obj, attach_port)
144               make_level(spec[1:], prototypes[1:], cache, "cpu_side")
145     else:
146          # we just built the MemTest objects
147          parent.cpu = objs
148          for t in objs:
149               t.test = getattr(attach_obj, attach_port)
150               t.functional = system.funcmem.port
151
152make_level(treespec, prototypes, system.physmem, "port")
153
154# -----------------------
155# run simulation
156# -----------------------
157
158root = Root( system = system )
159if options.atomic:
160    root.system.mem_mode = 'atomic'
161else:
162    root.system.mem_mode = 'timing'
163
164# Not much point in this being higher than the L1 latency
165m5.ticks.setGlobalFrequency('1ns')
166
167# instantiate configuration
168m5.instantiate(root)
169
170# simulate until program terminates
171exit_event = m5.simulate(options.maxtick)
172
173print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
174