memtest.py revision 4626
14467Sstever@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
23354Srdreslin@umich.edu# All rights reserved.
33354Srdreslin@umich.edu#
43354Srdreslin@umich.edu# Redistribution and use in source and binary forms, with or without
53354Srdreslin@umich.edu# modification, are permitted provided that the following conditions are
63354Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright
73354Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer;
83354Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright
93354Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the
103354Srdreslin@umich.edu# documentation and/or other materials provided with the distribution;
113354Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its
123354Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from
133354Srdreslin@umich.edu# this software without specific prior written permission.
143354Srdreslin@umich.edu#
153354Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
163354Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
173354Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
183354Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
193354Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
203354Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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233354Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
243354Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
253354Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
263354Srdreslin@umich.edu#
273354Srdreslin@umich.edu# Authors: Ron Dreslinski
283354Srdreslin@umich.edu
293354Srdreslin@umich.eduimport m5
303354Srdreslin@umich.edufrom m5.objects import *
313354Srdreslin@umich.eduimport os, optparse, sys
323354Srdreslin@umich.edum5.AddToPath('../common')
333354Srdreslin@umich.edu
343354Srdreslin@umich.eduparser = optparse.OptionParser()
353354Srdreslin@umich.edu
364626Sstever@eecs.umich.eduparser.add_option("-c", "--cache-levels", type="int", default=2,
374626Sstever@eecs.umich.edu                  metavar="LEVELS",
384626Sstever@eecs.umich.edu                  help="Number of cache levels [default: %default]")
394626Sstever@eecs.umich.eduparser.add_option("-a", "--atomic", action="store_true",
404626Sstever@eecs.umich.edu                  help="Use atomic (non-timing) mode")
414626Sstever@eecs.umich.eduparser.add_option("-b", "--blocking", action="store_true",
424626Sstever@eecs.umich.edu                  help="Use blocking caches")
434626Sstever@eecs.umich.eduparser.add_option("-l", "--maxloads", default="1G", metavar="N",
444626Sstever@eecs.umich.edu                  help="Stop after N loads [default: %default]")
454626Sstever@eecs.umich.eduparser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
464626Sstever@eecs.umich.edu                  metavar="T",
474626Sstever@eecs.umich.edu                  help="Stop after T ticks")
484626Sstever@eecs.umich.eduparser.add_option("-n", "--numtesters", type="int", default=8,
494626Sstever@eecs.umich.edu                  metavar="N",
504626Sstever@eecs.umich.edu                  help="Number of tester pseudo-CPUs [default: %default]")
514626Sstever@eecs.umich.eduparser.add_option("-p", "--protocol", default="moesi",
524626Sstever@eecs.umich.edu                  help="Coherence protocol [default: %default]")
534626Sstever@eecs.umich.edu
544626Sstever@eecs.umich.eduparser.add_option("-f", "--functional", type="int", default=0,
554626Sstever@eecs.umich.edu                  metavar="PCT",
564626Sstever@eecs.umich.edu                  help="Target percentage of functional accesses "
574626Sstever@eecs.umich.edu                  "[default: %default]")
584626Sstever@eecs.umich.eduparser.add_option("-u", "--uncacheable", type="int", default=0,
594626Sstever@eecs.umich.edu                  metavar="PCT",
604626Sstever@eecs.umich.edu                  help="Target percentage of uncacheable accesses "
614626Sstever@eecs.umich.edu                  "[default: %default]")
623354Srdreslin@umich.edu
633354Srdreslin@umich.edu(options, args) = parser.parse_args()
643354Srdreslin@umich.edu
653354Srdreslin@umich.eduif args:
663354Srdreslin@umich.edu     print "Error: script doesn't take any positional arguments"
673354Srdreslin@umich.edu     sys.exit(1)
683354Srdreslin@umich.edu
694626Sstever@eecs.umich.edu# Should generalize this someday... would be cool to have a loop that
704626Sstever@eecs.umich.edu# just iterates, adding a level of caching each time.
714626Sstever@eecs.umich.edu#if options.cache_levels != 2 and options.cache_levels != 0:
724626Sstever@eecs.umich.edu#     print "Error: number of cache levels must be 0 or 2"
734626Sstever@eecs.umich.edu#     sys.exit(1)
744626Sstever@eecs.umich.edu
754626Sstever@eecs.umich.eduif options.blocking:
764626Sstever@eecs.umich.edu     num_l1_mshrs = 1
774626Sstever@eecs.umich.edu     num_l2_mshrs = 1
784626Sstever@eecs.umich.eduelse:
794626Sstever@eecs.umich.edu     num_l1_mshrs = 12
804626Sstever@eecs.umich.edu     num_l2_mshrs = 92
814626Sstever@eecs.umich.edu
824626Sstever@eecs.umich.edublock_size = 64
834626Sstever@eecs.umich.edu
843354Srdreslin@umich.edu# --------------------
853354Srdreslin@umich.edu# Base L1 Cache
863354Srdreslin@umich.edu# ====================
873354Srdreslin@umich.edu
883354Srdreslin@umich.educlass L1(BaseCache):
894467Sstever@eecs.umich.edu    latency = '1ns'
904626Sstever@eecs.umich.edu    block_size = block_size
914626Sstever@eecs.umich.edu    mshrs = num_l1_mshrs
923354Srdreslin@umich.edu    tgts_per_mshr = 8
933354Srdreslin@umich.edu    protocol = CoherenceProtocol(protocol=options.protocol)
943354Srdreslin@umich.edu
953354Srdreslin@umich.edu# ----------------------
963354Srdreslin@umich.edu# Base L2 Cache
973354Srdreslin@umich.edu# ----------------------
983354Srdreslin@umich.edu
993354Srdreslin@umich.educlass L2(BaseCache):
1004626Sstever@eecs.umich.edu    block_size = block_size
1014467Sstever@eecs.umich.edu    latency = '10ns'
1024626Sstever@eecs.umich.edu    mshrs = num_l2_mshrs
1033354Srdreslin@umich.edu    tgts_per_mshr = 16
1043354Srdreslin@umich.edu    write_buffers = 8
1054626Sstever@eecs.umich.edu    protocol = CoherenceProtocol(protocol=options.protocol)
1063354Srdreslin@umich.edu
1074626Sstever@eecs.umich.eduif options.numtesters > block_size:
1084626Sstever@eecs.umich.edu     print "Error: Number of testers limited to %s because of false sharing" \
1094626Sstever@eecs.umich.edu           % (block_size)
1104626Sstever@eecs.umich.edu     sys.exit(1)
1113354Srdreslin@umich.edu
1124626Sstever@eecs.umich.educpus = [ MemTest(atomic=options.atomic, max_loads=options.maxloads,
1134626Sstever@eecs.umich.edu                 percent_functional=options.functional,
1144626Sstever@eecs.umich.edu                 percent_uncacheable=options.uncacheable,
1154467Sstever@eecs.umich.edu                 progress_interval=1000)
1164467Sstever@eecs.umich.edu         for i in xrange(options.numtesters) ]
1174467Sstever@eecs.umich.edu
1183354Srdreslin@umich.edu# system simulated
1193354Srdreslin@umich.edusystem = System(cpu = cpus, funcmem = PhysicalMemory(),
1204626Sstever@eecs.umich.edu                physmem = PhysicalMemory(latency = "100ns"),
1214476Sstever@eecs.umich.edu                membus = Bus(clock="500MHz", width=16))
1223354Srdreslin@umich.edu
1233354Srdreslin@umich.edu# l2cache & bus
1244626Sstever@eecs.umich.eduif options.cache_levels == 2:
1254476Sstever@eecs.umich.edu    system.toL2Bus = Bus(clock="500MHz", width=16)
1263354Srdreslin@umich.edu    system.l2c = L2(size='64kB', assoc=8)
1273354Srdreslin@umich.edu    system.l2c.cpu_side = system.toL2Bus.port
1283354Srdreslin@umich.edu
1293354Srdreslin@umich.edu    # connect l2c to membus
1303354Srdreslin@umich.edu    system.l2c.mem_side = system.membus.port
1313354Srdreslin@umich.edu
1323354Srdreslin@umich.edu# add L1 caches
1333354Srdreslin@umich.edufor cpu in cpus:
1344626Sstever@eecs.umich.edu    if options.cache_levels == 2:
1353354Srdreslin@umich.edu         cpu.l1c = L1(size = '32kB', assoc = 4)
1363354Srdreslin@umich.edu         cpu.test = cpu.l1c.cpu_side
1373354Srdreslin@umich.edu         cpu.l1c.mem_side = system.toL2Bus.port
1384626Sstever@eecs.umich.edu    elif options.cache_levels == 1:
1394626Sstever@eecs.umich.edu         cpu.l1c = L1(size = '32kB', assoc = 4)
1404626Sstever@eecs.umich.edu         cpu.test = cpu.l1c.cpu_side
1414626Sstever@eecs.umich.edu         cpu.l1c.mem_side = system.membus.port
1423354Srdreslin@umich.edu    else:
1433354Srdreslin@umich.edu         cpu.test = system.membus.port
1444467Sstever@eecs.umich.edu    system.funcmem.port = cpu.functional
1453354Srdreslin@umich.edu
1463354Srdreslin@umich.edu# connect memory to membus
1473354Srdreslin@umich.edusystem.physmem.port = system.membus.port
1483354Srdreslin@umich.edu
1493354Srdreslin@umich.edu
1503354Srdreslin@umich.edu# -----------------------
1513354Srdreslin@umich.edu# run simulation
1523354Srdreslin@umich.edu# -----------------------
1533354Srdreslin@umich.edu
1543354Srdreslin@umich.eduroot = Root( system = system )
1554626Sstever@eecs.umich.eduif options.atomic:
1564626Sstever@eecs.umich.edu    root.system.mem_mode = 'atomic'
1574626Sstever@eecs.umich.eduelse:
1583354Srdreslin@umich.edu    root.system.mem_mode = 'timing'
1593354Srdreslin@umich.edu
1604476Sstever@eecs.umich.edu# Not much point in this being higher than the L1 latency
1614476Sstever@eecs.umich.edum5.ticks.setGlobalFrequency('1ns')
1624476Sstever@eecs.umich.edu
1633354Srdreslin@umich.edu# instantiate configuration
1643354Srdreslin@umich.edum5.instantiate(root)
1653354Srdreslin@umich.edu
1663354Srdreslin@umich.edu# simulate until program terminates
1674626Sstever@eecs.umich.eduexit_event = m5.simulate(options.maxtick)
1683354Srdreslin@umich.edu
1693354Srdreslin@umich.eduprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
170