memtest.py revision 4476
12SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 21762SN/A# All rights reserved. 32SN/A# 42SN/A# Redistribution and use in source and binary forms, with or without 52SN/A# modification, are permitted provided that the following conditions are 62SN/A# met: redistributions of source code must retain the above copyright 72SN/A# notice, this list of conditions and the following disclaimer; 82SN/A# redistributions in binary form must reproduce the above copyright 92SN/A# notice, this list of conditions and the following disclaimer in the 102SN/A# documentation and/or other materials provided with the distribution; 112SN/A# neither the name of the copyright holders nor the names of its 122SN/A# contributors may be used to endorse or promote products derived from 132SN/A# this software without specific prior written permission. 142SN/A# 152SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262SN/A# 272665Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.eduimport m5 302SN/Afrom m5.objects import * 312SN/Aimport os, optparse, sys 322SN/Am5.AddToPath('../common') 332SN/A 342SN/Aparser = optparse.OptionParser() 352SN/A 362SN/Aparser.add_option("--caches", action="store_true") 37298SN/Aparser.add_option("-t", "--timing", action="store_true") 38298SN/Aparser.add_option("-m", "--maxtick", type="int") 392667Sstever@eecs.umich.eduparser.add_option("-l", "--maxloads", default = "1000000000000", type="int") 402SN/Aparser.add_option("-n", "--numtesters", default = "8", type="int") 412SN/Aparser.add_option("-p", "--protocol", 422667Sstever@eecs.umich.edu default="moesi", 432667Sstever@eecs.umich.edu help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)") 442SN/A 452SN/A(options, args) = parser.parse_args() 462667Sstever@eecs.umich.edu 472667Sstever@eecs.umich.eduif args: 482667Sstever@eecs.umich.edu print "Error: script doesn't take any positional arguments" 492667Sstever@eecs.umich.edu sys.exit(1) 502667Sstever@eecs.umich.edu 512667Sstever@eecs.umich.edu# -------------------- 522667Sstever@eecs.umich.edu# Base L1 Cache 532667Sstever@eecs.umich.edu# ==================== 542667Sstever@eecs.umich.edu 552667Sstever@eecs.umich.educlass L1(BaseCache): 562667Sstever@eecs.umich.edu latency = '1ns' 572SN/A block_size = 64 582SN/A mshrs = 12 59 tgts_per_mshr = 8 60 protocol = CoherenceProtocol(protocol=options.protocol) 61 62# ---------------------- 63# Base L2 Cache 64# ---------------------- 65 66class L2(BaseCache): 67 block_size = 64 68 latency = '10ns' 69 mshrs = 92 70 tgts_per_mshr = 16 71 write_buffers = 8 72 73#MAX CORES IS 8 with the false sharing method 74if options.numtesters > 8: 75 print "Error: NUmber of testers limited to 8 because of false sharing" 76 sys,exit(1) 77 78cpus = [ MemTest(atomic=not options.timing, max_loads=options.maxloads, 79 percent_functional=50, percent_uncacheable=10, 80 progress_interval=1000) 81 for i in xrange(options.numtesters) ] 82 83# system simulated 84system = System(cpu = cpus, funcmem = PhysicalMemory(), 85 physmem = PhysicalMemory(latency = "50ps"), 86 membus = Bus(clock="500MHz", width=16)) 87 88# l2cache & bus 89if options.caches: 90 system.toL2Bus = Bus(clock="500MHz", width=16) 91 system.l2c = L2(size='64kB', assoc=8) 92 system.l2c.cpu_side = system.toL2Bus.port 93 94 # connect l2c to membus 95 system.l2c.mem_side = system.membus.port 96 97# add L1 caches 98for cpu in cpus: 99 if options.caches: 100 cpu.l1c = L1(size = '32kB', assoc = 4) 101 cpu.test = cpu.l1c.cpu_side 102 cpu.l1c.mem_side = system.toL2Bus.port 103 else: 104 cpu.test = system.membus.port 105 system.funcmem.port = cpu.functional 106 107# connect memory to membus 108system.physmem.port = system.membus.port 109 110 111# ----------------------- 112# run simulation 113# ----------------------- 114 115root = Root( system = system ) 116if options.timing: 117 root.system.mem_mode = 'timing' 118else: 119 root.system.mem_mode = 'atomic' 120 121# Not much point in this being higher than the L1 latency 122m5.ticks.setGlobalFrequency('1ns') 123 124# instantiate configuration 125m5.instantiate(root) 126 127# simulate until program terminates 128if options.maxtick: 129 exit_event = m5.simulate(options.maxtick) 130else: 131 exit_event = m5.simulate(10000000000000) 132 133print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 134