memtest.py revision 3354
13354Srdreslin@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 23354Srdreslin@umich.edu# All rights reserved. 33354Srdreslin@umich.edu# 43354Srdreslin@umich.edu# Redistribution and use in source and binary forms, with or without 53354Srdreslin@umich.edu# modification, are permitted provided that the following conditions are 63354Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright 73354Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer; 83354Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright 93354Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the 103354Srdreslin@umich.edu# documentation and/or other materials provided with the distribution; 113354Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its 123354Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from 133354Srdreslin@umich.edu# this software without specific prior written permission. 143354Srdreslin@umich.edu# 153354Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163354Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173354Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183354Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193354Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203354Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213354Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223354Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233354Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243354Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253354Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263354Srdreslin@umich.edu# 273354Srdreslin@umich.edu# Authors: Ron Dreslinski 283354Srdreslin@umich.edu 293354Srdreslin@umich.eduimport m5 303354Srdreslin@umich.edufrom m5.objects import * 313354Srdreslin@umich.eduimport os, optparse, sys 323354Srdreslin@umich.edum5.AddToPath('../common') 333354Srdreslin@umich.edu 343354Srdreslin@umich.eduparser = optparse.OptionParser() 353354Srdreslin@umich.edu 363354Srdreslin@umich.eduparser.add_option("--caches", action="store_true") 373354Srdreslin@umich.eduparser.add_option("-t", "--timing", action="store_true") 383354Srdreslin@umich.eduparser.add_option("-m", "--maxtick", type="int") 393354Srdreslin@umich.eduparser.add_option("-l", "--maxloads", default = "1000000000000", type="int") 403354Srdreslin@umich.eduparser.add_option("-n", "--numtesters", default = "8", type="int") 413354Srdreslin@umich.eduparser.add_option("-p", "--protocol", 423354Srdreslin@umich.edu default="moesi", 433354Srdreslin@umich.edu help="The coherence protocol to use for the L1'a (i.e. MOESI, MOSI)") 443354Srdreslin@umich.edu 453354Srdreslin@umich.edu(options, args) = parser.parse_args() 463354Srdreslin@umich.edu 473354Srdreslin@umich.eduif args: 483354Srdreslin@umich.edu print "Error: script doesn't take any positional arguments" 493354Srdreslin@umich.edu sys.exit(1) 503354Srdreslin@umich.edu 513354Srdreslin@umich.edu# -------------------- 523354Srdreslin@umich.edu# Base L1 Cache 533354Srdreslin@umich.edu# ==================== 543354Srdreslin@umich.edu 553354Srdreslin@umich.educlass L1(BaseCache): 563354Srdreslin@umich.edu latency = 1 573354Srdreslin@umich.edu block_size = 64 583354Srdreslin@umich.edu mshrs = 12 593354Srdreslin@umich.edu tgts_per_mshr = 8 603354Srdreslin@umich.edu protocol = CoherenceProtocol(protocol=options.protocol) 613354Srdreslin@umich.edu 623354Srdreslin@umich.edu# ---------------------- 633354Srdreslin@umich.edu# Base L2 Cache 643354Srdreslin@umich.edu# ---------------------- 653354Srdreslin@umich.edu 663354Srdreslin@umich.educlass L2(BaseCache): 673354Srdreslin@umich.edu block_size = 64 683354Srdreslin@umich.edu latency = 10 693354Srdreslin@umich.edu mshrs = 92 703354Srdreslin@umich.edu tgts_per_mshr = 16 713354Srdreslin@umich.edu write_buffers = 8 723354Srdreslin@umich.edu 733354Srdreslin@umich.edu#MAX CORES IS 8 with the false sharing method 743354Srdreslin@umich.eduif options.numtesters > 8: 753354Srdreslin@umich.edu print "Error: NUmber of testers limited to 8 because of false sharing" 763354Srdreslin@umich.edu sys,exit(1) 773354Srdreslin@umich.edu 783354Srdreslin@umich.eduif options.timing: 793354Srdreslin@umich.edu cpus = [ MemTest(atomic=False, max_loads=options.maxloads, percent_functional=50, 803354Srdreslin@umich.edu percent_uncacheable=10, progress_interval=1000) 813354Srdreslin@umich.edu for i in xrange(options.numtesters) ] 823354Srdreslin@umich.eduelse: 833354Srdreslin@umich.edu cpus = [ MemTest(atomic=True, max_loads=options.maxloads, percent_functional=50, 843354Srdreslin@umich.edu percent_uncacheable=10, progress_interval=1000) 853354Srdreslin@umich.edu for i in xrange(options.numtesters) ] 863354Srdreslin@umich.edu# system simulated 873354Srdreslin@umich.edusystem = System(cpu = cpus, funcmem = PhysicalMemory(), 883354Srdreslin@umich.edu physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16)) 893354Srdreslin@umich.edu 903354Srdreslin@umich.edu# l2cache & bus 913354Srdreslin@umich.eduif options.caches: 923354Srdreslin@umich.edu system.toL2Bus = Bus(clock="500GHz", width=16) 933354Srdreslin@umich.edu system.l2c = L2(size='64kB', assoc=8) 943354Srdreslin@umich.edu system.l2c.cpu_side = system.toL2Bus.port 953354Srdreslin@umich.edu 963354Srdreslin@umich.edu # connect l2c to membus 973354Srdreslin@umich.edu system.l2c.mem_side = system.membus.port 983354Srdreslin@umich.edu 993354Srdreslin@umich.eduwhich_port = 0 1003354Srdreslin@umich.edu# add L1 caches 1013354Srdreslin@umich.edufor cpu in cpus: 1023354Srdreslin@umich.edu if options.caches: 1033354Srdreslin@umich.edu cpu.l1c = L1(size = '32kB', assoc = 4) 1043354Srdreslin@umich.edu cpu.test = cpu.l1c.cpu_side 1053354Srdreslin@umich.edu cpu.l1c.mem_side = system.toL2Bus.port 1063354Srdreslin@umich.edu else: 1073354Srdreslin@umich.edu cpu.test = system.membus.port 1083354Srdreslin@umich.edu if which_port == 0: 1093354Srdreslin@umich.edu system.funcmem.port = cpu.functional 1103354Srdreslin@umich.edu which_port = 1 1113354Srdreslin@umich.edu else: 1123354Srdreslin@umich.edu system.funcmem.functional = cpu.functional 1133354Srdreslin@umich.edu 1143354Srdreslin@umich.edu 1153354Srdreslin@umich.edu# connect memory to membus 1163354Srdreslin@umich.edusystem.physmem.port = system.membus.port 1173354Srdreslin@umich.edu 1183354Srdreslin@umich.edu 1193354Srdreslin@umich.edu# ----------------------- 1203354Srdreslin@umich.edu# run simulation 1213354Srdreslin@umich.edu# ----------------------- 1223354Srdreslin@umich.edu 1233354Srdreslin@umich.eduroot = Root( system = system ) 1243354Srdreslin@umich.eduif options.timing: 1253354Srdreslin@umich.edu root.system.mem_mode = 'timing' 1263354Srdreslin@umich.eduelse: 1273354Srdreslin@umich.edu root.system.mem_mode = 'atomic' 1283354Srdreslin@umich.edu 1293354Srdreslin@umich.edu# instantiate configuration 1303354Srdreslin@umich.edum5.instantiate(root) 1313354Srdreslin@umich.edu 1323354Srdreslin@umich.edu# simulate until program terminates 1333354Srdreslin@umich.eduif options.maxtick: 1343354Srdreslin@umich.edu exit_event = m5.simulate(options.maxtick) 1353354Srdreslin@umich.eduelse: 1363354Srdreslin@umich.edu exit_event = m5.simulate() 1373354Srdreslin@umich.edu 1383354Srdreslin@umich.eduprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 139