memtest.py revision 11200
110690Sandreas.hansson@arm.com# Copyright (c) 2015 ARM Limited 210690Sandreas.hansson@arm.com# All rights reserved. 310690Sandreas.hansson@arm.com# 410690Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 510690Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 610690Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 710690Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 810690Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 910690Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 1010690Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 1110690Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 1210690Sandreas.hansson@arm.com# 134467Sstever@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 143354Srdreslin@umich.edu# All rights reserved. 153354Srdreslin@umich.edu# 163354Srdreslin@umich.edu# Redistribution and use in source and binary forms, with or without 173354Srdreslin@umich.edu# modification, are permitted provided that the following conditions are 183354Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright 193354Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer; 203354Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright 213354Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the 223354Srdreslin@umich.edu# documentation and/or other materials provided with the distribution; 233354Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its 243354Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from 253354Srdreslin@umich.edu# this software without specific prior written permission. 263354Srdreslin@umich.edu# 273354Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283354Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293354Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303354Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313354Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323354Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333354Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343354Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353354Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363354Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373354Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383354Srdreslin@umich.edu# 393354Srdreslin@umich.edu# Authors: Ron Dreslinski 4010690Sandreas.hansson@arm.com# Andreas Hansson 413354Srdreslin@umich.edu 426654Snate@binkert.orgimport optparse 4310750Sandreas.hansson@arm.comimport random 446654Snate@binkert.orgimport sys 456654Snate@binkert.org 463354Srdreslin@umich.eduimport m5 473354Srdreslin@umich.edufrom m5.objects import * 483354Srdreslin@umich.edu 4910750Sandreas.hansson@arm.com# This example script stress tests the memory system by creating false 5010750Sandreas.hansson@arm.com# sharing in a tree topology. At the bottom of the tree is a shared 5110750Sandreas.hansson@arm.com# memory, and then at each level a number of testers are attached, 5210750Sandreas.hansson@arm.com# along with a number of caches that them selves fan out to subtrees 5310750Sandreas.hansson@arm.com# of testers and caches. Thus, it is possible to create a system with 5410750Sandreas.hansson@arm.com# arbitrarily deep cache hierarchies, sharing or no sharing of caches, 5510750Sandreas.hansson@arm.com# and testers not only at the L1s, but also at the L2s, L3s etc. 5610750Sandreas.hansson@arm.com 573354Srdreslin@umich.eduparser = optparse.OptionParser() 583354Srdreslin@umich.edu 594626Sstever@eecs.umich.eduparser.add_option("-a", "--atomic", action="store_true", 604626Sstever@eecs.umich.edu help="Use atomic (non-timing) mode") 614626Sstever@eecs.umich.eduparser.add_option("-b", "--blocking", action="store_true", 624626Sstever@eecs.umich.edu help="Use blocking caches") 634893Sstever@eecs.umich.eduparser.add_option("-l", "--maxloads", metavar="N", default=0, 644892Sstever@eecs.umich.edu help="Stop after N loads") 654626Sstever@eecs.umich.eduparser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 664626Sstever@eecs.umich.edu metavar="T", 674626Sstever@eecs.umich.edu help="Stop after T ticks") 684626Sstever@eecs.umich.edu 6910690Sandreas.hansson@arm.com# The tree specification consists of two colon-separated lists of one 7010690Sandreas.hansson@arm.com# or more integers, one for the caches, and one for the testers. The 7110690Sandreas.hansson@arm.com# first integer is the number of caches/testers closest to main 7210690Sandreas.hansson@arm.com# memory. Each cache then fans out to a subtree. The last integer in 7310690Sandreas.hansson@arm.com# the list is the number of caches/testers associated with the 7410690Sandreas.hansson@arm.com# uppermost level of memory. The other integers (if any) specify the 7510690Sandreas.hansson@arm.com# number of caches/testers connected at each level of the crossbar 7610690Sandreas.hansson@arm.com# hierarchy. The tester string should have one element more than the 7710690Sandreas.hansson@arm.com# cache string as there should always be testers attached to the 7810690Sandreas.hansson@arm.com# uppermost caches. 7910690Sandreas.hansson@arm.com 8010690Sandreas.hansson@arm.comparser.add_option("-c", "--caches", type="string", default="2:2:1", 8110690Sandreas.hansson@arm.com help="Colon-separated cache hierarchy specification, " 824892Sstever@eecs.umich.edu "see script comments for details " 834892Sstever@eecs.umich.edu "[default: %default]") 8410690Sandreas.hansson@arm.comparser.add_option("-t", "--testers", type="string", default="1:1:0:2", 8510690Sandreas.hansson@arm.com help="Colon-separated tester hierarchy specification, " 8610690Sandreas.hansson@arm.com "see script comments for details " 8710690Sandreas.hansson@arm.com "[default: %default]") 884626Sstever@eecs.umich.eduparser.add_option("-f", "--functional", type="int", default=0, 894626Sstever@eecs.umich.edu metavar="PCT", 904626Sstever@eecs.umich.edu help="Target percentage of functional accesses " 914626Sstever@eecs.umich.edu "[default: %default]") 924626Sstever@eecs.umich.eduparser.add_option("-u", "--uncacheable", type="int", default=0, 934626Sstever@eecs.umich.edu metavar="PCT", 944626Sstever@eecs.umich.edu help="Target percentage of uncacheable accesses " 954626Sstever@eecs.umich.edu "[default: %default]") 9610750Sandreas.hansson@arm.comparser.add_option("-r", "--random", action="store_true", 9710750Sandreas.hansson@arm.com help="Generate a random tree topology") 9810750Sandreas.hansson@arm.comparser.add_option("--progress", type="int", default=100000, 994628Sstever@eecs.umich.edu metavar="NLOADS", 1004628Sstever@eecs.umich.edu help="Progress message interval " 1014628Sstever@eecs.umich.edu "[default: %default]") 1029928SAli.Saidi@ARM.comparser.add_option("--sys-clock", action="store", type="string", 1039928SAli.Saidi@ARM.com default='1GHz', 1049928SAli.Saidi@ARM.com help = """Top-level clock for blocks running at system 1059928SAli.Saidi@ARM.com speed""") 1064628Sstever@eecs.umich.edu 1073354Srdreslin@umich.edu(options, args) = parser.parse_args() 1083354Srdreslin@umich.edu 1093354Srdreslin@umich.eduif args: 1103354Srdreslin@umich.edu print "Error: script doesn't take any positional arguments" 1113354Srdreslin@umich.edu sys.exit(1) 1123354Srdreslin@umich.edu 11310750Sandreas.hansson@arm.com# Get the total number of testers 11410750Sandreas.hansson@arm.comdef numtesters(cachespec, testerspec): 11510750Sandreas.hansson@arm.com # Determine the tester multiplier for each level as the 11610750Sandreas.hansson@arm.com # elements are per subsystem and it fans out 11710750Sandreas.hansson@arm.com multiplier = [1] 11810750Sandreas.hansson@arm.com for c in cachespec: 11910750Sandreas.hansson@arm.com multiplier.append(multiplier[-1] * c) 12010750Sandreas.hansson@arm.com 12110750Sandreas.hansson@arm.com total = 0 12210750Sandreas.hansson@arm.com for t, m in zip(testerspec, multiplier): 12310750Sandreas.hansson@arm.com total += t * m 12410750Sandreas.hansson@arm.com 12510750Sandreas.hansson@arm.com return total 12610750Sandreas.hansson@arm.com 1274626Sstever@eecs.umich.edublock_size = 64 1284626Sstever@eecs.umich.edu 12910705Sandreas.hansson@arm.com# Start by parsing the command line options and do some basic sanity 13010690Sandreas.hansson@arm.com# checking 13110750Sandreas.hansson@arm.comif options.random: 13210750Sandreas.hansson@arm.com # Generate a tree with a valid number of testers 13310750Sandreas.hansson@arm.com while True: 13410750Sandreas.hansson@arm.com tree_depth = random.randint(1, 4) 13510750Sandreas.hansson@arm.com cachespec = [random.randint(1, 3) for i in range(tree_depth)] 13610750Sandreas.hansson@arm.com testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)] 13710750Sandreas.hansson@arm.com if numtesters(cachespec, testerspec) < block_size: 13810750Sandreas.hansson@arm.com break 1393354Srdreslin@umich.edu 14010750Sandreas.hansson@arm.com print "Generated random tree -c", ':'.join(map(str, cachespec)), \ 14110750Sandreas.hansson@arm.com "-t", ':'.join(map(str, testerspec)) 14210750Sandreas.hansson@arm.comelse: 14310750Sandreas.hansson@arm.com try: 14410750Sandreas.hansson@arm.com cachespec = [int(x) for x in options.caches.split(':')] 14510750Sandreas.hansson@arm.com testerspec = [int(x) for x in options.testers.split(':')] 14610750Sandreas.hansson@arm.com except: 14710750Sandreas.hansson@arm.com print "Error: Unable to parse caches or testers option" 14810690Sandreas.hansson@arm.com sys.exit(1) 14910690Sandreas.hansson@arm.com 15010750Sandreas.hansson@arm.com if len(cachespec) < 1: 15110750Sandreas.hansson@arm.com print "Error: Must have at least one level of caches" 15210690Sandreas.hansson@arm.com sys.exit(1) 15310690Sandreas.hansson@arm.com 15410750Sandreas.hansson@arm.com if len(cachespec) != len(testerspec) - 1: 15510750Sandreas.hansson@arm.com print "Error: Testers must have one element more than caches" 15610750Sandreas.hansson@arm.com sys.exit(1) 15710690Sandreas.hansson@arm.com 15810750Sandreas.hansson@arm.com if testerspec[-1] == 0: 15910750Sandreas.hansson@arm.com print "Error: Must have testers at the uppermost level" 16010750Sandreas.hansson@arm.com sys.exit(1) 16110690Sandreas.hansson@arm.com 16210750Sandreas.hansson@arm.com for t in testerspec: 16310750Sandreas.hansson@arm.com if t < 0: 16410750Sandreas.hansson@arm.com print "Error: Cannot have a negative number of testers" 16510750Sandreas.hansson@arm.com sys.exit(1) 16610750Sandreas.hansson@arm.com 16710750Sandreas.hansson@arm.com for c in cachespec: 16810750Sandreas.hansson@arm.com if c < 1: 16910750Sandreas.hansson@arm.com print "Error: Must have 1 or more caches at each level" 17010750Sandreas.hansson@arm.com sys.exit(1) 17110750Sandreas.hansson@arm.com 17210750Sandreas.hansson@arm.com if numtesters(cachespec, testerspec) > block_size: 17310750Sandreas.hansson@arm.com print "Error: Limited to %s testers because of false sharing" \ 17410750Sandreas.hansson@arm.com % (block_size) 17510750Sandreas.hansson@arm.com sys.exit(1) 1763354Srdreslin@umich.edu 17710690Sandreas.hansson@arm.com# Define a prototype L1 cache that we scale for all successive levels 17811053Sandreas.hansson@arm.comproto_l1 = Cache(size = '32kB', assoc = 4, 17911053Sandreas.hansson@arm.com hit_latency = 1, response_latency = 1, 18011200Sandreas.hansson@arm.com tgts_per_mshr = 8, clusivity = 'mostly_incl', 18111200Sandreas.hansson@arm.com writeback_clean = True) 1824890Sstever@eecs.umich.edu 1834890Sstever@eecs.umich.eduif options.blocking: 1844890Sstever@eecs.umich.edu proto_l1.mshrs = 1 1854890Sstever@eecs.umich.eduelse: 1867656Ssteve.reinhardt@amd.com proto_l1.mshrs = 4 1874890Sstever@eecs.umich.edu 18810690Sandreas.hansson@arm.comcache_proto = [proto_l1] 1894890Sstever@eecs.umich.edu 19010690Sandreas.hansson@arm.com# Now add additional cache levels (if any) by scaling L1 params, the 19110690Sandreas.hansson@arm.com# first element is Ln, and the last element L1 19210690Sandreas.hansson@arm.comfor scale in cachespec[:-1]: 19310690Sandreas.hansson@arm.com # Clone previous level and update params 19410690Sandreas.hansson@arm.com prev = cache_proto[0] 1954890Sstever@eecs.umich.edu next = prev() 1967656Ssteve.reinhardt@amd.com next.size = prev.size * scale 19710270Sradhika.jagtap@ARM.com next.hit_latency = prev.hit_latency * 10 19810270Sradhika.jagtap@ARM.com next.response_latency = prev.response_latency * 10 1997656Ssteve.reinhardt@amd.com next.assoc = prev.assoc * scale 2007656Ssteve.reinhardt@amd.com next.mshrs = prev.mshrs * scale 20111198Sandreas.hansson@arm.com 20211198Sandreas.hansson@arm.com # Swap the inclusivity/exclusivity at each level. L2 is mostly 20311198Sandreas.hansson@arm.com # exclusive with respect to L1, L3 mostly inclusive, L4 mostly 20411198Sandreas.hansson@arm.com # exclusive etc. 20511200Sandreas.hansson@arm.com next.writeback_clean = not prev.writeback_clean 20611198Sandreas.hansson@arm.com if (prev.clusivity.value == 'mostly_incl'): 20711198Sandreas.hansson@arm.com next.clusivity = 'mostly_excl' 20811198Sandreas.hansson@arm.com else: 20911198Sandreas.hansson@arm.com next.clusivity = 'mostly_incl' 21011198Sandreas.hansson@arm.com 21110690Sandreas.hansson@arm.com cache_proto.insert(0, next) 2124467Sstever@eecs.umich.edu 21310690Sandreas.hansson@arm.com# Make a prototype for the tester to be used throughout 21410690Sandreas.hansson@arm.comproto_tester = MemTest(max_loads = options.maxloads, 21510690Sandreas.hansson@arm.com percent_functional = options.functional, 21610690Sandreas.hansson@arm.com percent_uncacheable = options.uncacheable, 21710690Sandreas.hansson@arm.com progress_interval = options.progress) 21810690Sandreas.hansson@arm.com 21910690Sandreas.hansson@arm.com# Set up the system along with a simple memory and reference memory 22010690Sandreas.hansson@arm.comsystem = System(physmem = SimpleMemory(), 2219815SAndreas Hansson <andreas.hansson> cache_line_size = block_size) 2229928SAli.Saidi@ARM.com 2239928SAli.Saidi@ARM.comsystem.voltage_domain = VoltageDomain(voltage = '1V') 2249928SAli.Saidi@ARM.com 2259928SAli.Saidi@ARM.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 2269928SAli.Saidi@ARM.com voltage_domain = system.voltage_domain) 2273354Srdreslin@umich.edu 22810690Sandreas.hansson@arm.com# For each level, track the next subsys index to use 22910690Sandreas.hansson@arm.comnext_subsys_index = [0] * (len(cachespec) + 1) 23010690Sandreas.hansson@arm.com 23110690Sandreas.hansson@arm.com# Recursive function to create a sub-tree of the cache and tester 23210690Sandreas.hansson@arm.com# hierarchy 23310690Sandreas.hansson@arm.comdef make_cache_level(ncaches, prototypes, level, next_cache): 23410690Sandreas.hansson@arm.com global next_subsys_index, proto_l1, testerspec, proto_tester 23510690Sandreas.hansson@arm.com 23610690Sandreas.hansson@arm.com index = next_subsys_index[level] 23710690Sandreas.hansson@arm.com next_subsys_index[level] += 1 23810690Sandreas.hansson@arm.com 23910690Sandreas.hansson@arm.com # Create a subsystem to contain the crossbar and caches, and 24010690Sandreas.hansson@arm.com # any testers 24110690Sandreas.hansson@arm.com subsys = SubSystem() 24210690Sandreas.hansson@arm.com setattr(system, 'l%dsubsys%d' % (level, index), subsys) 24310690Sandreas.hansson@arm.com 24410690Sandreas.hansson@arm.com # The levels are indexing backwards through the list 24510690Sandreas.hansson@arm.com ntesters = testerspec[len(cachespec) - level] 24610690Sandreas.hansson@arm.com 24710690Sandreas.hansson@arm.com # Scale the progress threshold as testers higher up in the tree 24810690Sandreas.hansson@arm.com # (smaller level) get a smaller portion of the overall bandwidth, 24910690Sandreas.hansson@arm.com # and also make the interval of packet injection longer for the 25010690Sandreas.hansson@arm.com # testers closer to the memory (larger level) to prevent them 25110690Sandreas.hansson@arm.com # hogging all the bandwidth 25210750Sandreas.hansson@arm.com limit = (len(cachespec) - level + 1) * 100000000 25310690Sandreas.hansson@arm.com testers = [proto_tester(interval = 10 * (level * level + 1), 25410690Sandreas.hansson@arm.com progress_check = limit) \ 25510690Sandreas.hansson@arm.com for i in xrange(ntesters)] 25610690Sandreas.hansson@arm.com if ntesters: 25710690Sandreas.hansson@arm.com subsys.tester = testers 25810690Sandreas.hansson@arm.com 25910690Sandreas.hansson@arm.com if level != 0: 26010690Sandreas.hansson@arm.com # Create a crossbar and add it to the subsystem, note that 26110690Sandreas.hansson@arm.com # we do this even with a single element on this level 26210720Sandreas.hansson@arm.com xbar = L2XBar() 26310690Sandreas.hansson@arm.com subsys.xbar = xbar 26410690Sandreas.hansson@arm.com if next_cache: 26510690Sandreas.hansson@arm.com xbar.master = next_cache.cpu_side 26610690Sandreas.hansson@arm.com 26710690Sandreas.hansson@arm.com # Create and connect the caches, both the ones fanning out 26810690Sandreas.hansson@arm.com # to create the tree, and the ones used to connect testers 26910690Sandreas.hansson@arm.com # on this level 27010690Sandreas.hansson@arm.com tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 27110690Sandreas.hansson@arm.com tester_caches = [proto_l1() for i in xrange(ntesters)] 27210690Sandreas.hansson@arm.com 27310690Sandreas.hansson@arm.com subsys.cache = tester_caches + tree_caches 27410690Sandreas.hansson@arm.com for cache in tree_caches: 27510690Sandreas.hansson@arm.com cache.mem_side = xbar.slave 27610690Sandreas.hansson@arm.com make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 27710690Sandreas.hansson@arm.com for tester, cache in zip(testers, tester_caches): 27810690Sandreas.hansson@arm.com tester.port = cache.cpu_side 27910690Sandreas.hansson@arm.com cache.mem_side = xbar.slave 28010690Sandreas.hansson@arm.com else: 28110690Sandreas.hansson@arm.com if not next_cache: 28210690Sandreas.hansson@arm.com print "Error: No next-level cache at top level" 28310690Sandreas.hansson@arm.com sys.exit(1) 28410690Sandreas.hansson@arm.com 28510690Sandreas.hansson@arm.com if ntesters > 1: 28610690Sandreas.hansson@arm.com # Create a crossbar and add it to the subsystem 28710720Sandreas.hansson@arm.com xbar = L2XBar() 28810690Sandreas.hansson@arm.com subsys.xbar = xbar 28910690Sandreas.hansson@arm.com xbar.master = next_cache.cpu_side 29010690Sandreas.hansson@arm.com for tester in testers: 29110690Sandreas.hansson@arm.com tester.port = xbar.slave 2928847Sandreas.hansson@arm.com else: 29310690Sandreas.hansson@arm.com # Single tester 29410690Sandreas.hansson@arm.com testers[0].port = next_cache.cpu_side 2953354Srdreslin@umich.edu 29610690Sandreas.hansson@arm.com# Top level call to create the cache hierarchy, bottom up 29710690Sandreas.hansson@arm.commake_cache_level(cachespec, cache_proto, len(cachespec), None) 2983354Srdreslin@umich.edu 29910690Sandreas.hansson@arm.com# Connect the lowest level crossbar to the memory 30010690Sandreas.hansson@arm.comlast_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 30110690Sandreas.hansson@arm.comlast_subsys.xbar.master = system.physmem.port 3023354Srdreslin@umich.edu 30310690Sandreas.hansson@arm.comroot = Root(full_system = False, system = system) 3044626Sstever@eecs.umich.eduif options.atomic: 3054626Sstever@eecs.umich.edu root.system.mem_mode = 'atomic' 3064626Sstever@eecs.umich.eduelse: 3073354Srdreslin@umich.edu root.system.mem_mode = 'timing' 3083354Srdreslin@umich.edu 3098847Sandreas.hansson@arm.com# The system port is never used in the tester so merely connect it 3108847Sandreas.hansson@arm.com# to avoid problems 31110690Sandreas.hansson@arm.comroot.system.system_port = last_subsys.xbar.slave 3128847Sandreas.hansson@arm.com 31310690Sandreas.hansson@arm.com# Instantiate configuration 3147525Ssteve.reinhardt@amd.comm5.instantiate() 3153354Srdreslin@umich.edu 31610690Sandreas.hansson@arm.com# Simulate until program terminates 3174626Sstever@eecs.umich.eduexit_event = m5.simulate(options.maxtick) 3183354Srdreslin@umich.edu 3193354Srdreslin@umich.eduprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 320