memtest.py revision 10690
110690Sandreas.hansson@arm.com# Copyright (c) 2015 ARM Limited 210690Sandreas.hansson@arm.com# All rights reserved. 310690Sandreas.hansson@arm.com# 410690Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 510690Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 610690Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 710690Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 810690Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 910690Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 1010690Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 1110690Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 1210690Sandreas.hansson@arm.com# 134467Sstever@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 143354Srdreslin@umich.edu# All rights reserved. 153354Srdreslin@umich.edu# 163354Srdreslin@umich.edu# Redistribution and use in source and binary forms, with or without 173354Srdreslin@umich.edu# modification, are permitted provided that the following conditions are 183354Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright 193354Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer; 203354Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright 213354Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the 223354Srdreslin@umich.edu# documentation and/or other materials provided with the distribution; 233354Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its 243354Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from 253354Srdreslin@umich.edu# this software without specific prior written permission. 263354Srdreslin@umich.edu# 273354Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283354Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293354Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303354Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313354Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323354Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333354Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343354Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353354Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363354Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373354Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383354Srdreslin@umich.edu# 393354Srdreslin@umich.edu# Authors: Ron Dreslinski 4010690Sandreas.hansson@arm.com# Andreas Hansson 413354Srdreslin@umich.edu 426654Snate@binkert.orgimport optparse 436654Snate@binkert.orgimport sys 446654Snate@binkert.org 453354Srdreslin@umich.eduimport m5 463354Srdreslin@umich.edufrom m5.objects import * 473354Srdreslin@umich.edu 483354Srdreslin@umich.eduparser = optparse.OptionParser() 493354Srdreslin@umich.edu 504626Sstever@eecs.umich.eduparser.add_option("-a", "--atomic", action="store_true", 514626Sstever@eecs.umich.edu help="Use atomic (non-timing) mode") 524626Sstever@eecs.umich.eduparser.add_option("-b", "--blocking", action="store_true", 534626Sstever@eecs.umich.edu help="Use blocking caches") 544893Sstever@eecs.umich.eduparser.add_option("-l", "--maxloads", metavar="N", default=0, 554892Sstever@eecs.umich.edu help="Stop after N loads") 564626Sstever@eecs.umich.eduparser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 574626Sstever@eecs.umich.edu metavar="T", 584626Sstever@eecs.umich.edu help="Stop after T ticks") 594626Sstever@eecs.umich.edu 6010690Sandreas.hansson@arm.com# This example script stress tests the memory system by creating false 6110690Sandreas.hansson@arm.com# sharing in a tree topology. At the bottom of the tree is a shared 6210690Sandreas.hansson@arm.com# memory, and then at each level a number of testers are attached, 6310690Sandreas.hansson@arm.com# along with a number of caches that them selves fan out to subtrees 6410690Sandreas.hansson@arm.com# of testers and caches. Thus, it is possible to create a system with 6510690Sandreas.hansson@arm.com# arbitrarily deep cache hierarchies, sharing or no sharing of caches, 6610690Sandreas.hansson@arm.com# and testers not only at the L1s, but also at the L2s, L3s etc. 674892Sstever@eecs.umich.edu# 6810690Sandreas.hansson@arm.com# The tree specification consists of two colon-separated lists of one 6910690Sandreas.hansson@arm.com# or more integers, one for the caches, and one for the testers. The 7010690Sandreas.hansson@arm.com# first integer is the number of caches/testers closest to main 7110690Sandreas.hansson@arm.com# memory. Each cache then fans out to a subtree. The last integer in 7210690Sandreas.hansson@arm.com# the list is the number of caches/testers associated with the 7310690Sandreas.hansson@arm.com# uppermost level of memory. The other integers (if any) specify the 7410690Sandreas.hansson@arm.com# number of caches/testers connected at each level of the crossbar 7510690Sandreas.hansson@arm.com# hierarchy. The tester string should have one element more than the 7610690Sandreas.hansson@arm.com# cache string as there should always be testers attached to the 7710690Sandreas.hansson@arm.com# uppermost caches. 7810690Sandreas.hansson@arm.com 7910690Sandreas.hansson@arm.comparser.add_option("-c", "--caches", type="string", default="2:2:1", 8010690Sandreas.hansson@arm.com help="Colon-separated cache hierarchy specification, " 814892Sstever@eecs.umich.edu "see script comments for details " 824892Sstever@eecs.umich.edu "[default: %default]") 8310690Sandreas.hansson@arm.comparser.add_option("-t", "--testers", type="string", default="1:1:0:2", 8410690Sandreas.hansson@arm.com help="Colon-separated tester hierarchy specification, " 8510690Sandreas.hansson@arm.com "see script comments for details " 8610690Sandreas.hansson@arm.com "[default: %default]") 874626Sstever@eecs.umich.eduparser.add_option("-f", "--functional", type="int", default=0, 884626Sstever@eecs.umich.edu metavar="PCT", 894626Sstever@eecs.umich.edu help="Target percentage of functional accesses " 904626Sstever@eecs.umich.edu "[default: %default]") 914626Sstever@eecs.umich.eduparser.add_option("-u", "--uncacheable", type="int", default=0, 924626Sstever@eecs.umich.edu metavar="PCT", 934626Sstever@eecs.umich.edu help="Target percentage of uncacheable accesses " 944626Sstever@eecs.umich.edu "[default: %default]") 953354Srdreslin@umich.edu 9610690Sandreas.hansson@arm.comparser.add_option("--progress", type="int", default=10000, 974628Sstever@eecs.umich.edu metavar="NLOADS", 984628Sstever@eecs.umich.edu help="Progress message interval " 994628Sstever@eecs.umich.edu "[default: %default]") 1009928SAli.Saidi@ARM.comparser.add_option("--sys-clock", action="store", type="string", 1019928SAli.Saidi@ARM.com default='1GHz', 1029928SAli.Saidi@ARM.com help = """Top-level clock for blocks running at system 1039928SAli.Saidi@ARM.com speed""") 1044628Sstever@eecs.umich.edu 1053354Srdreslin@umich.edu(options, args) = parser.parse_args() 1063354Srdreslin@umich.edu 1073354Srdreslin@umich.eduif args: 1083354Srdreslin@umich.edu print "Error: script doesn't take any positional arguments" 1093354Srdreslin@umich.edu sys.exit(1) 1103354Srdreslin@umich.edu 1114626Sstever@eecs.umich.edublock_size = 64 1124626Sstever@eecs.umich.edu 11310690Sandreas.hansson@arm.com# Start by partins the command line options and do some basic sanity 11410690Sandreas.hansson@arm.com# checking 1154892Sstever@eecs.umich.edutry: 11610690Sandreas.hansson@arm.com cachespec = [int(x) for x in options.caches.split(':')] 11710690Sandreas.hansson@arm.com testerspec = [int(x) for x in options.testers.split(':')] 1184892Sstever@eecs.umich.eduexcept: 11910690Sandreas.hansson@arm.com print "Error: Unable to parse caches or testers option" 1204892Sstever@eecs.umich.edu sys.exit(1) 1213354Srdreslin@umich.edu 12210690Sandreas.hansson@arm.comif len(cachespec) < 1: 12310690Sandreas.hansson@arm.com print "Error: Must have at least one level of caches" 12410690Sandreas.hansson@arm.com sys.exit(1) 12510690Sandreas.hansson@arm.com 12610690Sandreas.hansson@arm.comif len(cachespec) != len(testerspec) - 1: 12710690Sandreas.hansson@arm.com print "Error: Testers must have one element more than caches" 12810690Sandreas.hansson@arm.com sys.exit(1) 12910690Sandreas.hansson@arm.com 13010690Sandreas.hansson@arm.comif testerspec[-1] == 0: 13110690Sandreas.hansson@arm.com print "Error: Must have testers at the uppermost level" 13210690Sandreas.hansson@arm.com sys.exit(1) 13310690Sandreas.hansson@arm.com 13410690Sandreas.hansson@arm.comfor t in testerspec: 13510690Sandreas.hansson@arm.com if t < 0: 13610690Sandreas.hansson@arm.com print "Error: Cannot have a negative number of testers" 13710690Sandreas.hansson@arm.com sys.exit(1) 13810690Sandreas.hansson@arm.com 13910690Sandreas.hansson@arm.comfor c in cachespec: 14010690Sandreas.hansson@arm.com if c < 1: 14110690Sandreas.hansson@arm.com print "Error: Must have 1 or more caches at each level" 14210690Sandreas.hansson@arm.com sys.exit(1) 14310690Sandreas.hansson@arm.com 14410690Sandreas.hansson@arm.com# Determine the tester multiplier for each level as the string 14510690Sandreas.hansson@arm.com# elements are per subsystem and it fans out 14610690Sandreas.hansson@arm.commultiplier = [1] 14710690Sandreas.hansson@arm.comfor c in cachespec: 14810690Sandreas.hansson@arm.com if c < 1: 14910690Sandreas.hansson@arm.com print "Error: Must have at least one cache per level" 15010690Sandreas.hansson@arm.com multiplier.append(multiplier[-1] * c) 15110690Sandreas.hansson@arm.com 15210690Sandreas.hansson@arm.comnumtesters = 0 15310690Sandreas.hansson@arm.comfor t, m in zip(testerspec, multiplier): 15410690Sandreas.hansson@arm.com numtesters += t * m 15510690Sandreas.hansson@arm.com 1564890Sstever@eecs.umich.eduif numtesters > block_size: 1574626Sstever@eecs.umich.edu print "Error: Number of testers limited to %s because of false sharing" \ 1584626Sstever@eecs.umich.edu % (block_size) 1594626Sstever@eecs.umich.edu sys.exit(1) 1603354Srdreslin@umich.edu 16110690Sandreas.hansson@arm.com# Define a prototype L1 cache that we scale for all successive levels 1629815SAndreas Hansson <andreas.hansson>proto_l1 = BaseCache(size = '32kB', assoc = 4, 1639928SAli.Saidi@ARM.com hit_latency = 1, response_latency = 1, 16410690Sandreas.hansson@arm.com tgts_per_mshr = 8, is_top_level = True) 1654890Sstever@eecs.umich.edu 1664890Sstever@eecs.umich.eduif options.blocking: 1674890Sstever@eecs.umich.edu proto_l1.mshrs = 1 1684890Sstever@eecs.umich.eduelse: 1697656Ssteve.reinhardt@amd.com proto_l1.mshrs = 4 1704890Sstever@eecs.umich.edu 17110690Sandreas.hansson@arm.comcache_proto = [proto_l1] 1724890Sstever@eecs.umich.edu 17310690Sandreas.hansson@arm.com# Now add additional cache levels (if any) by scaling L1 params, the 17410690Sandreas.hansson@arm.com# first element is Ln, and the last element L1 17510690Sandreas.hansson@arm.comfor scale in cachespec[:-1]: 17610690Sandreas.hansson@arm.com # Clone previous level and update params 17710690Sandreas.hansson@arm.com prev = cache_proto[0] 1784890Sstever@eecs.umich.edu next = prev() 1797656Ssteve.reinhardt@amd.com next.size = prev.size * scale 18010270Sradhika.jagtap@ARM.com next.hit_latency = prev.hit_latency * 10 18110270Sradhika.jagtap@ARM.com next.response_latency = prev.response_latency * 10 1827656Ssteve.reinhardt@amd.com next.assoc = prev.assoc * scale 1837656Ssteve.reinhardt@amd.com next.mshrs = prev.mshrs * scale 18410690Sandreas.hansson@arm.com next.is_top_level = False 18510690Sandreas.hansson@arm.com cache_proto.insert(0, next) 1864467Sstever@eecs.umich.edu 18710690Sandreas.hansson@arm.com# Make a prototype for the tester to be used throughout 18810690Sandreas.hansson@arm.comproto_tester = MemTest(max_loads = options.maxloads, 18910690Sandreas.hansson@arm.com percent_functional = options.functional, 19010690Sandreas.hansson@arm.com percent_uncacheable = options.uncacheable, 19110690Sandreas.hansson@arm.com progress_interval = options.progress) 19210690Sandreas.hansson@arm.com 19310690Sandreas.hansson@arm.com# Set up the system along with a simple memory and reference memory 19410690Sandreas.hansson@arm.comsystem = System(physmem = SimpleMemory(), 1959815SAndreas Hansson <andreas.hansson> cache_line_size = block_size) 1969928SAli.Saidi@ARM.com 1979928SAli.Saidi@ARM.comsystem.voltage_domain = VoltageDomain(voltage = '1V') 1989928SAli.Saidi@ARM.com 1999928SAli.Saidi@ARM.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 2009928SAli.Saidi@ARM.com voltage_domain = system.voltage_domain) 2013354Srdreslin@umich.edu 20210690Sandreas.hansson@arm.com# For each level, track the next subsys index to use 20310690Sandreas.hansson@arm.comnext_subsys_index = [0] * (len(cachespec) + 1) 20410690Sandreas.hansson@arm.com 20510690Sandreas.hansson@arm.com# Recursive function to create a sub-tree of the cache and tester 20610690Sandreas.hansson@arm.com# hierarchy 20710690Sandreas.hansson@arm.comdef make_cache_level(ncaches, prototypes, level, next_cache): 20810690Sandreas.hansson@arm.com global next_subsys_index, proto_l1, testerspec, proto_tester 20910690Sandreas.hansson@arm.com 21010690Sandreas.hansson@arm.com index = next_subsys_index[level] 21110690Sandreas.hansson@arm.com next_subsys_index[level] += 1 21210690Sandreas.hansson@arm.com 21310690Sandreas.hansson@arm.com # Create a subsystem to contain the crossbar and caches, and 21410690Sandreas.hansson@arm.com # any testers 21510690Sandreas.hansson@arm.com subsys = SubSystem() 21610690Sandreas.hansson@arm.com setattr(system, 'l%dsubsys%d' % (level, index), subsys) 21710690Sandreas.hansson@arm.com 21810690Sandreas.hansson@arm.com # The levels are indexing backwards through the list 21910690Sandreas.hansson@arm.com ntesters = testerspec[len(cachespec) - level] 22010690Sandreas.hansson@arm.com 22110690Sandreas.hansson@arm.com # Scale the progress threshold as testers higher up in the tree 22210690Sandreas.hansson@arm.com # (smaller level) get a smaller portion of the overall bandwidth, 22310690Sandreas.hansson@arm.com # and also make the interval of packet injection longer for the 22410690Sandreas.hansson@arm.com # testers closer to the memory (larger level) to prevent them 22510690Sandreas.hansson@arm.com # hogging all the bandwidth 22610690Sandreas.hansson@arm.com limit = (len(cachespec) - level + 1) * 10000000 22710690Sandreas.hansson@arm.com testers = [proto_tester(interval = 10 * (level * level + 1), 22810690Sandreas.hansson@arm.com progress_check = limit) \ 22910690Sandreas.hansson@arm.com for i in xrange(ntesters)] 23010690Sandreas.hansson@arm.com if ntesters: 23110690Sandreas.hansson@arm.com subsys.tester = testers 23210690Sandreas.hansson@arm.com 23310690Sandreas.hansson@arm.com if level != 0: 23410690Sandreas.hansson@arm.com # Create a crossbar and add it to the subsystem, note that 23510690Sandreas.hansson@arm.com # we do this even with a single element on this level 23610690Sandreas.hansson@arm.com xbar = CoherentXBar(width = 32) 23710690Sandreas.hansson@arm.com subsys.xbar = xbar 23810690Sandreas.hansson@arm.com if next_cache: 23910690Sandreas.hansson@arm.com xbar.master = next_cache.cpu_side 24010690Sandreas.hansson@arm.com 24110690Sandreas.hansson@arm.com # Create and connect the caches, both the ones fanning out 24210690Sandreas.hansson@arm.com # to create the tree, and the ones used to connect testers 24310690Sandreas.hansson@arm.com # on this level 24410690Sandreas.hansson@arm.com tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 24510690Sandreas.hansson@arm.com tester_caches = [proto_l1() for i in xrange(ntesters)] 24610690Sandreas.hansson@arm.com 24710690Sandreas.hansson@arm.com subsys.cache = tester_caches + tree_caches 24810690Sandreas.hansson@arm.com for cache in tree_caches: 24910690Sandreas.hansson@arm.com cache.mem_side = xbar.slave 25010690Sandreas.hansson@arm.com make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 25110690Sandreas.hansson@arm.com for tester, cache in zip(testers, tester_caches): 25210690Sandreas.hansson@arm.com tester.port = cache.cpu_side 25310690Sandreas.hansson@arm.com cache.mem_side = xbar.slave 25410690Sandreas.hansson@arm.com else: 25510690Sandreas.hansson@arm.com if not next_cache: 25610690Sandreas.hansson@arm.com print "Error: No next-level cache at top level" 25710690Sandreas.hansson@arm.com sys.exit(1) 25810690Sandreas.hansson@arm.com 25910690Sandreas.hansson@arm.com if ntesters > 1: 26010690Sandreas.hansson@arm.com # Create a crossbar and add it to the subsystem 26110690Sandreas.hansson@arm.com xbar = CoherentXBar(width = 32) 26210690Sandreas.hansson@arm.com subsys.xbar = xbar 26310690Sandreas.hansson@arm.com xbar.master = next_cache.cpu_side 26410690Sandreas.hansson@arm.com for tester in testers: 26510690Sandreas.hansson@arm.com tester.port = xbar.slave 2668847Sandreas.hansson@arm.com else: 26710690Sandreas.hansson@arm.com # Single tester 26810690Sandreas.hansson@arm.com testers[0].port = next_cache.cpu_side 2693354Srdreslin@umich.edu 27010690Sandreas.hansson@arm.com# Top level call to create the cache hierarchy, bottom up 27110690Sandreas.hansson@arm.commake_cache_level(cachespec, cache_proto, len(cachespec), None) 2723354Srdreslin@umich.edu 27310690Sandreas.hansson@arm.com# Connect the lowest level crossbar to the memory 27410690Sandreas.hansson@arm.comlast_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 27510690Sandreas.hansson@arm.comlast_subsys.xbar.master = system.physmem.port 2763354Srdreslin@umich.edu 27710690Sandreas.hansson@arm.comroot = Root(full_system = False, system = system) 2784626Sstever@eecs.umich.eduif options.atomic: 2794626Sstever@eecs.umich.edu root.system.mem_mode = 'atomic' 2804626Sstever@eecs.umich.eduelse: 2813354Srdreslin@umich.edu root.system.mem_mode = 'timing' 2823354Srdreslin@umich.edu 2838847Sandreas.hansson@arm.com# The system port is never used in the tester so merely connect it 2848847Sandreas.hansson@arm.com# to avoid problems 28510690Sandreas.hansson@arm.comroot.system.system_port = last_subsys.xbar.slave 2868847Sandreas.hansson@arm.com 28710690Sandreas.hansson@arm.com# Instantiate configuration 2887525Ssteve.reinhardt@amd.comm5.instantiate() 2893354Srdreslin@umich.edu 29010690Sandreas.hansson@arm.com# Simulate until program terminates 2914626Sstever@eecs.umich.eduexit_event = m5.simulate(options.maxtick) 2923354Srdreslin@umich.edu 2933354Srdreslin@umich.eduprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 294