memcheck.py revision 11753:6aefb19ff369
15217Ssaidi@eecs.umich.edu# Copyright (c) 2015-2016 ARM Limited 212109SRekai.GonzalezAlberquilla@arm.com# All rights reserved. 39920Syasuko.eckert@amd.com# 49428SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 59428SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 69428SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 79428SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 89428SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 99428SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 109428SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 119428SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 129428SAndreas.Sandberg@ARM.com# 139428SAndreas.Sandberg@ARM.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 149428SAndreas.Sandberg@ARM.com# All rights reserved. 155217Ssaidi@eecs.umich.edu# 165217Ssaidi@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 175217Ssaidi@eecs.umich.edu# modification, are permitted provided that the following conditions are 185217Ssaidi@eecs.umich.edu# met: redistributions of source code must retain the above copyright 195217Ssaidi@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 205217Ssaidi@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 215217Ssaidi@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 225217Ssaidi@eecs.umich.edu# documentation and/or other materials provided with the distribution; 235217Ssaidi@eecs.umich.edu# neither the name of the copyright holders nor the names of its 245217Ssaidi@eecs.umich.edu# contributors may be used to endorse or promote products derived from 255217Ssaidi@eecs.umich.edu# this software without specific prior written permission. 265217Ssaidi@eecs.umich.edu# 275217Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 285217Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 295217Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 305217Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 315217Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 325217Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 335217Ssaidi@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 345217Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 355217Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 365217Ssaidi@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 375217Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 385217Ssaidi@eecs.umich.edu# 395217Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski 405217Ssaidi@eecs.umich.edu# Andreas Hansson 415217Ssaidi@eecs.umich.edu 425217Ssaidi@eecs.umich.eduimport optparse 435217Ssaidi@eecs.umich.eduimport random 4411793Sbrandon.potter@amd.comimport sys 4511793Sbrandon.potter@amd.com 4611627Smichael.lebeane@amd.comimport m5 4712334Sgabeblack@google.comfrom m5.objects import * 485217Ssaidi@eecs.umich.edu 496658Snate@binkert.orgparser = optparse.OptionParser() 509441SAndreas.Sandberg@ARM.com 519441SAndreas.Sandberg@ARM.comparser.add_option("-a", "--atomic", action="store_true", 528232Snate@binkert.org help="Use atomic (non-timing) mode") 5311627Smichael.lebeane@amd.comparser.add_option("-b", "--blocking", action="store_true", 5411627Smichael.lebeane@amd.com help="Use blocking caches") 559441SAndreas.Sandberg@ARM.comparser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 565217Ssaidi@eecs.umich.edu metavar="T", 575217Ssaidi@eecs.umich.edu help="Stop after T ticks") 585217Ssaidi@eecs.umich.eduparser.add_option("-p", "--prefetchers", action="store_true", 595217Ssaidi@eecs.umich.edu help="Use prefetchers") 605217Ssaidi@eecs.umich.eduparser.add_option("-s", "--stridepref", action="store_true", 615217Ssaidi@eecs.umich.edu help="Use strided prefetchers") 625217Ssaidi@eecs.umich.edu 635217Ssaidi@eecs.umich.edu# This example script has a lot in common with the memtest.py in that 645217Ssaidi@eecs.umich.edu# it is designed to stress tests the memory system. However, this 655217Ssaidi@eecs.umich.edu# script uses oblivious traffic generators to create the stimuli, and 665217Ssaidi@eecs.umich.edu# couples them with memcheckers to verify that the data read matches 675217Ssaidi@eecs.umich.edu# the allowed outcomes. Just like memtest.py, the traffic generators 685217Ssaidi@eecs.umich.edu# and checkers are placed in a tree topology. At the bottom of the 695217Ssaidi@eecs.umich.edu# tree is a shared memory, and then at each level a number of 705217Ssaidi@eecs.umich.edu# generators and checkers are attached, along with a number of caches 715217Ssaidi@eecs.umich.edu# that them selves fan out to subtrees of generators and caches. Thus, 725217Ssaidi@eecs.umich.edu# it is possible to create a system with arbitrarily deep cache 735217Ssaidi@eecs.umich.edu# hierarchies, sharing or no sharing of caches, and generators not 745217Ssaidi@eecs.umich.edu# only at the L1s, but also at the L2s, L3s etc. 755217Ssaidi@eecs.umich.edu# 765217Ssaidi@eecs.umich.edu# The tree specification consists of two colon-separated lists of one 775217Ssaidi@eecs.umich.edu# or more integers, one for the caches, and one for the 785217Ssaidi@eecs.umich.edu# testers/generators. The first integer is the number of 7912109SRekai.GonzalezAlberquilla@arm.com# caches/testers closest to main memory. Each cache then fans out to a 8012109SRekai.GonzalezAlberquilla@arm.com# subtree. The last integer in the list is the number of 8112109SRekai.GonzalezAlberquilla@arm.com# caches/testers associated with the uppermost level of memory. The 8212109SRekai.GonzalezAlberquilla@arm.com# other integers (if any) specify the number of caches/testers 8312109SRekai.GonzalezAlberquilla@arm.com# connected at each level of the crossbar hierarchy. The tester string 8412109SRekai.GonzalezAlberquilla@arm.com# should have one element more than the cache string as there should 8512109SRekai.GonzalezAlberquilla@arm.com# always be testers attached to the uppermost caches. 8612109SRekai.GonzalezAlberquilla@arm.com# 8712109SRekai.GonzalezAlberquilla@arm.com# Since this script tests actual sharing, there is also a possibility 8812109SRekai.GonzalezAlberquilla@arm.com# to stress prefetching and the interaction between prefetchers and 895217Ssaidi@eecs.umich.edu# caches. The traffic generators switch between random address streams 905217Ssaidi@eecs.umich.edu# and linear address streams to ensure that the prefetchers will 915217Ssaidi@eecs.umich.edu# trigger. By default prefetchers are off. 925217Ssaidi@eecs.umich.edu 935217Ssaidi@eecs.umich.eduparser.add_option("-c", "--caches", type="string", default="3:2", 945217Ssaidi@eecs.umich.edu help="Colon-separated cache hierarchy specification, " 955217Ssaidi@eecs.umich.edu "see script comments for details " 965217Ssaidi@eecs.umich.edu "[default: %default]") 979920Syasuko.eckert@amd.comparser.add_option("-t", "--testers", type="string", default="1:0:2", 989920Syasuko.eckert@amd.com help="Colon-separated tester hierarchy specification, " 999920Syasuko.eckert@amd.com "see script comments for details " 1009920Syasuko.eckert@amd.com "[default: %default]") 1019920Syasuko.eckert@amd.comparser.add_option("-r", "--random", action="store_true", 1029920Syasuko.eckert@amd.com help="Generate a random tree topology") 1039920Syasuko.eckert@amd.comparser.add_option("--sys-clock", action="store", type="string", 1049920Syasuko.eckert@amd.com default='1GHz', 1057720Sgblack@eecs.umich.edu help = """Top-level clock for blocks running at system 1067720Sgblack@eecs.umich.edu speed""") 1075712Shsul@eecs.umich.edu 1085712Shsul@eecs.umich.edu(options, args) = parser.parse_args() 1095217Ssaidi@eecs.umich.edu 1105217Ssaidi@eecs.umich.eduif args: 1115714Shsul@eecs.umich.edu print "Error: script doesn't take any positional arguments" 11211005Sandreas.sandberg@arm.com sys.exit(1) 11311005Sandreas.sandberg@arm.com 11411005Sandreas.sandberg@arm.com# Start by parsing the command line options and do some basic sanity 1155714Shsul@eecs.umich.edu# checking 1165714Shsul@eecs.umich.eduif options.random: 1175714Shsul@eecs.umich.edu # Generate a tree with a valid number of testers 1185217Ssaidi@eecs.umich.edu tree_depth = random.randint(1, 4) 1199428SAndreas.Sandberg@ARM.com cachespec = [random.randint(1, 3) for i in range(tree_depth)] 1209428SAndreas.Sandberg@ARM.com testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)] 12111627Smichael.lebeane@amd.com print "Generated random tree -c", ':'.join(map(str, cachespec)), \ 12211627Smichael.lebeane@amd.com "-t", ':'.join(map(str, testerspec)) 12311627Smichael.lebeane@amd.comelse: 12411627Smichael.lebeane@amd.com try: 12511627Smichael.lebeane@amd.com cachespec = [int(x) for x in options.caches.split(':')] 12611627Smichael.lebeane@amd.com testerspec = [int(x) for x in options.testers.split(':')] 12711627Smichael.lebeane@amd.com except: 12811627Smichael.lebeane@amd.com print "Error: Unable to parse caches or testers option" 12911627Smichael.lebeane@amd.com sys.exit(1) 13011627Smichael.lebeane@amd.com 13111627Smichael.lebeane@amd.com if len(cachespec) < 1: 13211627Smichael.lebeane@amd.com print "Error: Must have at least one level of caches" 13311627Smichael.lebeane@amd.com sys.exit(1) 13411627Smichael.lebeane@amd.com 13511627Smichael.lebeane@amd.com if len(cachespec) != len(testerspec) - 1: 13611627Smichael.lebeane@amd.com print "Error: Testers must have one element more than caches" 13711627Smichael.lebeane@amd.com sys.exit(1) 13811627Smichael.lebeane@amd.com 13911627Smichael.lebeane@amd.com if testerspec[-1] == 0: 14011627Smichael.lebeane@amd.com print "Error: Must have testers at the uppermost level" 14111627Smichael.lebeane@amd.com sys.exit(1) 14211627Smichael.lebeane@amd.com 14311627Smichael.lebeane@amd.com for t in testerspec: 14411627Smichael.lebeane@amd.com if t < 0: 14511627Smichael.lebeane@amd.com print "Error: Cannot have a negative number of testers" 14611627Smichael.lebeane@amd.com sys.exit(1) 14711627Smichael.lebeane@amd.com 14811627Smichael.lebeane@amd.com for c in cachespec: 14911627Smichael.lebeane@amd.com if c < 1: 15011627Smichael.lebeane@amd.com print "Error: Must have 1 or more caches at each level" 15111627Smichael.lebeane@amd.com sys.exit(1) 15211627Smichael.lebeane@amd.com 15311627Smichael.lebeane@amd.com# Determine the tester multiplier for each level as the string 15410905Sandreas.sandberg@arm.com# elements are per subsystem and it fans out 1559428SAndreas.Sandberg@ARM.commultiplier = [1] 1569428SAndreas.Sandberg@ARM.comfor c in cachespec: 1579428SAndreas.Sandberg@ARM.com if c < 1: 1589428SAndreas.Sandberg@ARM.com print "Error: Must have at least one cache per level" 1599428SAndreas.Sandberg@ARM.com multiplier.append(multiplier[-1] * c) 1609428SAndreas.Sandberg@ARM.com 1619428SAndreas.Sandberg@ARM.comnumtesters = 0 1629428SAndreas.Sandberg@ARM.comfor t, m in zip(testerspec, multiplier): 16310905Sandreas.sandberg@arm.com numtesters += t * m 1649428SAndreas.Sandberg@ARM.com 16512109SRekai.GonzalezAlberquilla@arm.com# Define a prototype L1 cache that we scale for all successive levels 16612109SRekai.GonzalezAlberquilla@arm.comproto_l1 = Cache(size = '32kB', assoc = 4, 16712109SRekai.GonzalezAlberquilla@arm.com tag_latency = 1, data_latency = 1, response_latency = 1, 16812109SRekai.GonzalezAlberquilla@arm.com tgts_per_mshr = 8) 16912109SRekai.GonzalezAlberquilla@arm.com 17012109SRekai.GonzalezAlberquilla@arm.comif options.blocking: 1719428SAndreas.Sandberg@ARM.com proto_l1.mshrs = 1 1729428SAndreas.Sandberg@ARM.comelse: 1739428SAndreas.Sandberg@ARM.com proto_l1.mshrs = 4 1749428SAndreas.Sandberg@ARM.com 1759428SAndreas.Sandberg@ARM.comif options.prefetchers: 1769920Syasuko.eckert@amd.com proto_l1.prefetcher = TaggedPrefetcher() 1779920Syasuko.eckert@amd.comelif options.stridepref: 1789920Syasuko.eckert@amd.com proto_l1.prefetcher = StridePrefetcher() 1799920Syasuko.eckert@amd.com 1809920Syasuko.eckert@amd.comcache_proto = [proto_l1] 1819920Syasuko.eckert@amd.com 1829920Syasuko.eckert@amd.com# Now add additional cache levels (if any) by scaling L1 params, the 18310905Sandreas.sandberg@arm.com# first element is Ln, and the last element L1 1849428SAndreas.Sandberg@ARM.comfor scale in cachespec[:-1]: 1859428SAndreas.Sandberg@ARM.com # Clone previous level and update params 1869428SAndreas.Sandberg@ARM.com prev = cache_proto[0] 1879428SAndreas.Sandberg@ARM.com next = prev() 1889428SAndreas.Sandberg@ARM.com next.size = prev.size * scale 18910905Sandreas.sandberg@arm.com next.tag_latency = prev.tag_latency * 10 1909428SAndreas.Sandberg@ARM.com next.data_latency = prev.data_latency * 10 1919428SAndreas.Sandberg@ARM.com next.response_latency = prev.response_latency * 10 1929428SAndreas.Sandberg@ARM.com next.assoc = prev.assoc * scale 1939428SAndreas.Sandberg@ARM.com next.mshrs = prev.mshrs * scale 1949428SAndreas.Sandberg@ARM.com cache_proto.insert(0, next) 1959428SAndreas.Sandberg@ARM.com 19610905Sandreas.sandberg@arm.com# Create a config to be used by all the traffic generators 1979428SAndreas.Sandberg@ARM.comcfg_file_name = "configs/example/memcheck.cfg" 1989428SAndreas.Sandberg@ARM.comcfg_file = open(cfg_file_name, 'w') 1999428SAndreas.Sandberg@ARM.com 20012109SRekai.GonzalezAlberquilla@arm.com# Three states, with random, linear and idle behaviours. The random 20112109SRekai.GonzalezAlberquilla@arm.com# and linear states access memory in the range [0 : 16 Mbyte] with 8 20212109SRekai.GonzalezAlberquilla@arm.com# byte and 64 byte accesses respectively. 20312109SRekai.GonzalezAlberquilla@arm.comcfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n") 20412109SRekai.GonzalezAlberquilla@arm.comcfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 64 50000 150000 0\n") 20512109SRekai.GonzalezAlberquilla@arm.comcfg_file.write("STATE 2 10000000 IDLE\n") 2069428SAndreas.Sandberg@ARM.comcfg_file.write("INIT 0\n") 2079428SAndreas.Sandberg@ARM.comcfg_file.write("TRANSITION 0 1 0.5\n") 2089428SAndreas.Sandberg@ARM.comcfg_file.write("TRANSITION 0 2 0.5\n") 2099428SAndreas.Sandberg@ARM.comcfg_file.write("TRANSITION 1 0 0.5\n") 2109428SAndreas.Sandberg@ARM.comcfg_file.write("TRANSITION 1 2 0.5\n") 2119920Syasuko.eckert@amd.comcfg_file.write("TRANSITION 2 0 0.5\n") 2129920Syasuko.eckert@amd.comcfg_file.write("TRANSITION 2 1 0.5\n") 2139920Syasuko.eckert@amd.comcfg_file.close() 2149920Syasuko.eckert@amd.com 2159920Syasuko.eckert@amd.com# Make a prototype for the tester to be used throughout 2169920Syasuko.eckert@amd.comproto_tester = TrafficGen(config_file = cfg_file_name) 2179920Syasuko.eckert@amd.com 2189428SAndreas.Sandberg@ARM.com# Set up the system along with a DRAM controller 21910905Sandreas.sandberg@arm.comsystem = System(physmem = DDR3_1600_x64()) 2209428SAndreas.Sandberg@ARM.com 2219428SAndreas.Sandberg@ARM.comsystem.voltage_domain = VoltageDomain(voltage = '1V') 2229428SAndreas.Sandberg@ARM.com 2239428SAndreas.Sandberg@ARM.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 2249441SAndreas.Sandberg@ARM.com voltage_domain = system.voltage_domain) 2259441SAndreas.Sandberg@ARM.com 2269441SAndreas.Sandberg@ARM.comsystem.memchecker = MemChecker() 2279441SAndreas.Sandberg@ARM.com 2289441SAndreas.Sandberg@ARM.com# For each level, track the next subsys index to use 2299441SAndreas.Sandberg@ARM.comnext_subsys_index = [0] * (len(cachespec) + 1) 2309441SAndreas.Sandberg@ARM.com 2319441SAndreas.Sandberg@ARM.com# Recursive function to create a sub-tree of the cache and tester 2329441SAndreas.Sandberg@ARM.com# hierarchy 2339441SAndreas.Sandberg@ARM.comdef make_cache_level(ncaches, prototypes, level, next_cache): 2349441SAndreas.Sandberg@ARM.com global next_subsys_index, proto_l1, testerspec, proto_tester 2359441SAndreas.Sandberg@ARM.com 2369441SAndreas.Sandberg@ARM.com index = next_subsys_index[level] 2379441SAndreas.Sandberg@ARM.com next_subsys_index[level] += 1 2389441SAndreas.Sandberg@ARM.com 2399441SAndreas.Sandberg@ARM.com # Create a subsystem to contain the crossbar and caches, and 2409441SAndreas.Sandberg@ARM.com # any testers 2419441SAndreas.Sandberg@ARM.com subsys = SubSystem() 2429441SAndreas.Sandberg@ARM.com setattr(system, 'l%dsubsys%d' % (level, index), subsys) 2439441SAndreas.Sandberg@ARM.com 2449441SAndreas.Sandberg@ARM.com # The levels are indexing backwards through the list 2459441SAndreas.Sandberg@ARM.com ntesters = testerspec[len(cachespec) - level] 2469441SAndreas.Sandberg@ARM.com 2479441SAndreas.Sandberg@ARM.com testers = [proto_tester() for i in xrange(ntesters)] 2489441SAndreas.Sandberg@ARM.com checkers = [MemCheckerMonitor(memchecker = system.memchecker) \ 2499441SAndreas.Sandberg@ARM.com for i in xrange(ntesters)] 2509441SAndreas.Sandberg@ARM.com if ntesters: 2519441SAndreas.Sandberg@ARM.com subsys.tester = testers 2529441SAndreas.Sandberg@ARM.com subsys.checkers = checkers 2539441SAndreas.Sandberg@ARM.com 2549441SAndreas.Sandberg@ARM.com if level != 0: 2559441SAndreas.Sandberg@ARM.com # Create a crossbar and add it to the subsystem, note that 2569441SAndreas.Sandberg@ARM.com # we do this even with a single element on this level 2579441SAndreas.Sandberg@ARM.com xbar = L2XBar(width = 32) 258 subsys.xbar = xbar 259 if next_cache: 260 xbar.master = next_cache.cpu_side 261 262 # Create and connect the caches, both the ones fanning out 263 # to create the tree, and the ones used to connect testers 264 # on this level 265 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 266 tester_caches = [proto_l1() for i in xrange(ntesters)] 267 268 subsys.cache = tester_caches + tree_caches 269 for cache in tree_caches: 270 cache.mem_side = xbar.slave 271 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 272 for tester, checker, cache in zip(testers, checkers, tester_caches): 273 tester.port = checker.slave 274 checker.master = cache.cpu_side 275 cache.mem_side = xbar.slave 276 else: 277 if not next_cache: 278 print "Error: No next-level cache at top level" 279 sys.exit(1) 280 281 if ntesters > 1: 282 # Create a crossbar and add it to the subsystem 283 xbar = L2XBar(width = 32) 284 subsys.xbar = xbar 285 xbar.master = next_cache.cpu_side 286 for tester, checker in zip(testers, checkers): 287 tester.port = checker.slave 288 checker.master = xbar.slave 289 else: 290 # Single tester 291 testers[0].port = checkers[0].slave 292 checkers[0].master = next_cache.cpu_side 293 294# Top level call to create the cache hierarchy, bottom up 295make_cache_level(cachespec, cache_proto, len(cachespec), None) 296 297# Connect the lowest level crossbar to the memory 298last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 299last_subsys.xbar.master = system.physmem.port 300last_subsys.xbar.point_of_coherency = True 301 302root = Root(full_system = False, system = system) 303if options.atomic: 304 root.system.mem_mode = 'atomic' 305else: 306 root.system.mem_mode = 'timing' 307 308# The system port is never used in the tester so merely connect it 309# to avoid problems 310root.system.system_port = last_subsys.xbar.slave 311 312# Instantiate configuration 313m5.instantiate() 314 315# Simulate until program terminates 316exit_event = m5.simulate(options.maxtick) 317 318print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 319