memcheck.py revision 10705:c6cb94a14fea
1# Copyright (c) 2015 ARM Limited
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38#
39# Authors: Ron Dreslinski
40#          Andreas Hansson
41
42import optparse
43import sys
44
45import m5
46from m5.objects import *
47
48parser = optparse.OptionParser()
49
50parser.add_option("-a", "--atomic", action="store_true",
51                  help="Use atomic (non-timing) mode")
52parser.add_option("-b", "--blocking", action="store_true",
53                  help="Use blocking caches")
54parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
55                  metavar="T",
56                  help="Stop after T ticks")
57parser.add_option("-p", "--prefetchers", action="store_true",
58                  help="Use prefetchers")
59parser.add_option("-s", "--stridepref", action="store_true",
60                  help="Use strided prefetchers")
61
62# This example script has a lot in common with the memtest.py in that
63# it is designed to stress tests the memory system. However, this
64# script uses oblivious traffic generators to create the stimuli, and
65# couples them with memcheckers to verify that the data read matches
66# the allowed outcomes. Just like memtest.py, the traffic generators
67# and checkers are placed in a tree topology. At the bottom of the
68# tree is a shared memory, and then at each level a number of
69# generators and checkers are attached, along with a number of caches
70# that them selves fan out to subtrees of generators and caches. Thus,
71# it is possible to create a system with arbitrarily deep cache
72# hierarchies, sharing or no sharing of caches, and generators not
73# only at the L1s, but also at the L2s, L3s etc.
74#
75# The tree specification consists of two colon-separated lists of one
76# or more integers, one for the caches, and one for the
77# testers/generators. The first integer is the number of
78# caches/testers closest to main memory. Each cache then fans out to a
79# subtree. The last integer in the list is the number of
80# caches/testers associated with the uppermost level of memory. The
81# other integers (if any) specify the number of caches/testers
82# connected at each level of the crossbar hierarchy. The tester string
83# should have one element more than the cache string as there should
84# always be testers attached to the uppermost caches.
85#
86# Since this script tests actual sharing, there is also a possibility
87# to stress prefetching and the interaction between prefetchers and
88# caches. The traffic generators switch between random address streams
89# and linear address streams to ensure that the prefetchers will
90# trigger. By default prefetchers are off.
91
92parser.add_option("-c", "--caches", type="string", default="3:2",
93                  help="Colon-separated cache hierarchy specification, "
94                  "see script comments for details "
95                  "[default: %default]")
96parser.add_option("-t", "--testers", type="string", default="1:0:2",
97                  help="Colon-separated tester hierarchy specification, "
98                  "see script comments for details "
99                  "[default: %default]")
100parser.add_option("--sys-clock", action="store", type="string",
101                  default='1GHz',
102                  help = """Top-level clock for blocks running at system
103                  speed""")
104
105(options, args) = parser.parse_args()
106
107if args:
108     print "Error: script doesn't take any positional arguments"
109     sys.exit(1)
110
111# Start by parsing the command line options and do some basic sanity
112# checking
113try:
114     cachespec = [int(x) for x in options.caches.split(':')]
115     testerspec = [int(x) for x in options.testers.split(':')]
116except:
117     print "Error: Unable to parse caches or testers option"
118     sys.exit(1)
119
120if len(cachespec) < 1:
121     print "Error: Must have at least one level of caches"
122     sys.exit(1)
123
124if len(cachespec) != len(testerspec) - 1:
125     print "Error: Testers must have one element more than caches"
126     sys.exit(1)
127
128if testerspec[-1] == 0:
129     print "Error: Must have testers at the uppermost level"
130     sys.exit(1)
131
132for t in testerspec:
133     if t < 0:
134          print "Error: Cannot have a negative number of testers"
135          sys.exit(1)
136
137for c in cachespec:
138     if c < 1:
139          print "Error: Must have 1 or more caches at each level"
140          sys.exit(1)
141
142# Determine the tester multiplier for each level as the string
143# elements are per subsystem and it fans out
144multiplier = [1]
145for c in cachespec:
146     if c < 1:
147          print "Error: Must have at least one cache per level"
148     multiplier.append(multiplier[-1] * c)
149
150numtesters = 0
151for t, m in zip(testerspec, multiplier):
152     numtesters += t * m
153
154# Define a prototype L1 cache that we scale for all successive levels
155proto_l1 = BaseCache(size = '32kB', assoc = 4,
156                     hit_latency = 1, response_latency = 1,
157                     tgts_per_mshr = 8, is_top_level = True)
158
159if options.blocking:
160     proto_l1.mshrs = 1
161else:
162     proto_l1.mshrs = 4
163
164if options.prefetchers:
165     proto_l1.prefetcher = TaggedPrefetcher()
166elif options.stridepref:
167     proto_l1.prefetcher = StridePrefetcher()
168
169cache_proto = [proto_l1]
170
171# Now add additional cache levels (if any) by scaling L1 params, the
172# first element is Ln, and the last element L1
173for scale in cachespec[:-1]:
174     # Clone previous level and update params
175     prev = cache_proto[0]
176     next = prev()
177     next.size = prev.size * scale
178     next.hit_latency = prev.hit_latency * 10
179     next.response_latency = prev.response_latency * 10
180     next.assoc = prev.assoc * scale
181     next.mshrs = prev.mshrs * scale
182     next.is_top_level = False
183     cache_proto.insert(0, next)
184
185# Create a config to be used by all the traffic generators
186cfg_file_name = "configs/example/memcheck.cfg"
187cfg_file = open(cfg_file_name, 'w')
188
189# Three states, with random, linear and idle behaviours. The random
190# and linear states access memory in the range [0 : 16 Mbyte] with 8
191# byte accesses.
192cfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n")
193cfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 8 50000 150000 0\n")
194cfg_file.write("STATE 2 10000000 IDLE\n")
195cfg_file.write("INIT 0\n")
196cfg_file.write("TRANSITION 0 1 0.5\n")
197cfg_file.write("TRANSITION 0 2 0.5\n")
198cfg_file.write("TRANSITION 1 0 0.5\n")
199cfg_file.write("TRANSITION 1 2 0.5\n")
200cfg_file.write("TRANSITION 2 0 0.5\n")
201cfg_file.write("TRANSITION 2 1 0.5\n")
202cfg_file.close()
203
204# Make a prototype for the tester to be used throughout
205proto_tester = TrafficGen(config_file = cfg_file_name)
206
207# Set up the system along with a DRAM controller
208system = System(physmem = DDR3_1600_x64())
209
210system.voltage_domain = VoltageDomain(voltage = '1V')
211
212system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
213                        voltage_domain = system.voltage_domain)
214
215system.memchecker = MemChecker()
216
217# For each level, track the next subsys index to use
218next_subsys_index = [0] * (len(cachespec) + 1)
219
220# Recursive function to create a sub-tree of the cache and tester
221# hierarchy
222def make_cache_level(ncaches, prototypes, level, next_cache):
223     global next_subsys_index, proto_l1, testerspec, proto_tester
224
225     index = next_subsys_index[level]
226     next_subsys_index[level] += 1
227
228     # Create a subsystem to contain the crossbar and caches, and
229     # any testers
230     subsys = SubSystem()
231     setattr(system, 'l%dsubsys%d' % (level, index), subsys)
232
233     # The levels are indexing backwards through the list
234     ntesters = testerspec[len(cachespec) - level]
235
236     testers = [proto_tester() for i in xrange(ntesters)]
237     checkers = [MemCheckerMonitor(memchecker = system.memchecker) \
238                      for i in xrange(ntesters)]
239     if ntesters:
240          subsys.tester = testers
241          subsys.checkers = checkers
242
243     if level != 0:
244          # Create a crossbar and add it to the subsystem, note that
245          # we do this even with a single element on this level
246          xbar = CoherentXBar(width = 32)
247          subsys.xbar = xbar
248          if next_cache:
249               xbar.master = next_cache.cpu_side
250
251          # Create and connect the caches, both the ones fanning out
252          # to create the tree, and the ones used to connect testers
253          # on this level
254          tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
255          tester_caches = [proto_l1() for i in xrange(ntesters)]
256
257          subsys.cache = tester_caches + tree_caches
258          for cache in tree_caches:
259               cache.mem_side = xbar.slave
260               make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
261          for tester, checker, cache in zip(testers, checkers, tester_caches):
262               tester.port = checker.slave
263               checker.master = cache.cpu_side
264               cache.mem_side = xbar.slave
265     else:
266          if not next_cache:
267               print "Error: No next-level cache at top level"
268               sys.exit(1)
269
270          if ntesters > 1:
271               # Create a crossbar and add it to the subsystem
272               xbar = CoherentXBar(width = 32)
273               subsys.xbar = xbar
274               xbar.master = next_cache.cpu_side
275               for tester, checker in zip(testers, checkers):
276                    tester.port = checker.slave
277                    checker.master = xbar.slave
278          else:
279               # Single tester
280               testers[0].port = checkers[0].slave
281               checkers[0].master = next_cache.cpu_side
282
283# Top level call to create the cache hierarchy, bottom up
284make_cache_level(cachespec, cache_proto, len(cachespec), None)
285
286# Connect the lowest level crossbar to the memory
287last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
288last_subsys.xbar.master = system.physmem.port
289
290root = Root(full_system = False, system = system)
291if options.atomic:
292    root.system.mem_mode = 'atomic'
293else:
294    root.system.mem_mode = 'timing'
295
296# The system port is never used in the tester so merely connect it
297# to avoid problems
298root.system.system_port = last_subsys.xbar.slave
299
300# Instantiate configuration
301m5.instantiate()
302
303# Simulate until program terminates
304exit_event = m5.simulate(options.maxtick)
305
306print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
307