memcheck.py revision 12564
18706Sandreas.hansson@arm.com# Copyright (c) 2015-2016 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 135369Ssaidi@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 143005Sstever@eecs.umich.edu# All rights reserved. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253005Sstever@eecs.umich.edu# this software without specific prior written permission. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383005Sstever@eecs.umich.edu# 393005Sstever@eecs.umich.edu# Authors: Ron Dreslinski 403005Sstever@eecs.umich.edu# Andreas Hansson 412710SN/A 422710SN/Afrom __future__ import print_function 433005Sstever@eecs.umich.edu 442889SN/Aimport optparse 456654Snate@binkert.orgimport random 466654Snate@binkert.orgimport sys 476654Snate@binkert.org 486654Snate@binkert.orgimport m5 496654Snate@binkert.orgfrom m5.objects import * 502667SN/A 516654Snate@binkert.orgparser = optparse.OptionParser() 526654Snate@binkert.org 536654Snate@binkert.orgparser.add_option("-a", "--atomic", action="store_true", 545457Ssaidi@eecs.umich.edu help="Use atomic (non-timing) mode") 556654Snate@binkert.orgparser.add_option("-b", "--blocking", action="store_true", 566654Snate@binkert.org help="Use blocking caches") 575457Ssaidi@eecs.umich.eduparser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick, 586654Snate@binkert.org metavar="T", 598169SLisa.Hsu@amd.com help="Stop after T ticks") 608169SLisa.Hsu@amd.comparser.add_option("-p", "--prefetchers", action="store_true", 618169SLisa.Hsu@amd.com help="Use prefetchers") 626654Snate@binkert.orgparser.add_option("-s", "--stridepref", action="store_true", 633395Shsul@eecs.umich.edu help="Use strided prefetchers") 646981SLisa.Hsu@amd.com 653448Shsul@eecs.umich.edu# This example script has a lot in common with the memtest.py in that 665369Ssaidi@eecs.umich.edu# it is designed to stress tests the memory system. However, this 673394Shsul@eecs.umich.edu# script uses oblivious traffic generators to create the stimuli, and 683444Sktlim@umich.edu# couples them with memcheckers to verify that the data read matches 693444Sktlim@umich.edu# the allowed outcomes. Just like memtest.py, the traffic generators 703444Sktlim@umich.edu# and checkers are placed in a tree topology. At the bottom of the 713444Sktlim@umich.edu# tree is a shared memory, and then at each level a number of 722424SN/A# generators and checkers are attached, along with a number of caches 732957SN/A# that them selves fan out to subtrees of generators and caches. Thus, 742957SN/A# it is possible to create a system with arbitrarily deep cache 753323Shsul@eecs.umich.edu# hierarchies, sharing or no sharing of caches, and generators not 763005Sstever@eecs.umich.edu# only at the L1s, but also at the L2s, L3s etc. 777787SAli.Saidi@ARM.com# 787787SAli.Saidi@ARM.com# The tree specification consists of two colon-separated lists of one 795514SMichael.Adler@intel.com# or more integers, one for the caches, and one for the 802957SN/A# testers/generators. The first integer is the number of 815514SMichael.Adler@intel.com# caches/testers closest to main memory. Each cache then fans out to a 825514SMichael.Adler@intel.com# subtree. The last integer in the list is the number of 835514SMichael.Adler@intel.com# caches/testers associated with the uppermost level of memory. The 845514SMichael.Adler@intel.com# other integers (if any) specify the number of caches/testers 858467Snilay@cs.wisc.edu# connected at each level of the crossbar hierarchy. The tester string 863444Sktlim@umich.edu# should have one element more than the cache string as there should 872957SN/A# always be testers attached to the uppermost caches. 888482Snilay@cs.wisc.edu# 898482Snilay@cs.wisc.edu# Since this script tests actual sharing, there is also a possibility 908482Snilay@cs.wisc.edu# to stress prefetching and the interaction between prefetchers and 918482Snilay@cs.wisc.edu# caches. The traffic generators switch between random address streams 928467Snilay@cs.wisc.edu# and linear address streams to ensure that the prefetchers will 932957SN/A# trigger. By default prefetchers are off. 942957SN/A 952957SN/Aparser.add_option("-c", "--caches", type="string", default="3:2", 962957SN/A help="Colon-separated cache hierarchy specification, " 972957SN/A "see script comments for details " 982957SN/A "[default: %default]") 998167SLisa.Hsu@amd.comparser.add_option("-t", "--testers", type="string", default="1:0:2", 1008167SLisa.Hsu@amd.com help="Colon-separated tester hierarchy specification, " 1018167SLisa.Hsu@amd.com "see script comments for details " 1025369Ssaidi@eecs.umich.edu "[default: %default]") 1038167SLisa.Hsu@amd.comparser.add_option("-r", "--random", action="store_true", 1048167SLisa.Hsu@amd.com help="Generate a random tree topology") 1058167SLisa.Hsu@amd.comparser.add_option("--sys-clock", action="store", type="string", 1068167SLisa.Hsu@amd.com default='1GHz', 1078167SLisa.Hsu@amd.com help = """Top-level clock for blocks running at system 1088167SLisa.Hsu@amd.com speed""") 1098167SLisa.Hsu@amd.com 1108168SLisa.Hsu@amd.com(options, args) = parser.parse_args() 1118168SLisa.Hsu@amd.com 1128168SLisa.Hsu@amd.comif args: 1138168SLisa.Hsu@amd.com print("Error: script doesn't take any positional arguments") 1148167SLisa.Hsu@amd.com sys.exit(1) 1158167SLisa.Hsu@amd.com 1168168SLisa.Hsu@amd.com# Start by parsing the command line options and do some basic sanity 1175369Ssaidi@eecs.umich.edu# checking 1185369Ssaidi@eecs.umich.eduif options.random: 1195369Ssaidi@eecs.umich.edu # Generate a tree with a valid number of testers 1205369Ssaidi@eecs.umich.edu tree_depth = random.randint(1, 4) 1215369Ssaidi@eecs.umich.edu cachespec = [random.randint(1, 3) for i in range(tree_depth)] 1228167SLisa.Hsu@amd.com testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)] 1235369Ssaidi@eecs.umich.edu print("Generated random tree -c", ':'.join(map(str, cachespec)), 1245369Ssaidi@eecs.umich.edu "-t", ':'.join(map(str, testerspec))) 1252801SN/Aelse: 1262801SN/A try: 1275514SMichael.Adler@intel.com cachespec = [int(x) for x in options.caches.split(':')] 1285514SMichael.Adler@intel.com testerspec = [int(x) for x in options.testers.split(':')] 1295514SMichael.Adler@intel.com except: 1305514SMichael.Adler@intel.com print("Error: Unable to parse caches or testers option") 1312418SN/A sys.exit(1) 1326391Sksewell@umich.edu 1336391Sksewell@umich.edu if len(cachespec) < 1: 1346391Sksewell@umich.edu print("Error: Must have at least one level of caches") 1356642Sksewell@umich.edu sys.exit(1) 1366391Sksewell@umich.edu 1378649Snilay@cs.wisc.edu if len(cachespec) != len(testerspec) - 1: 1382833SN/A print("Error: Testers must have one element more than caches") 1392833SN/A sys.exit(1) 1402833SN/A 1412833SN/A if testerspec[-1] == 0: 1422833SN/A print("Error: Must have testers at the uppermost level") 1432833SN/A sys.exit(1) 1445514SMichael.Adler@intel.com 1455514SMichael.Adler@intel.com for t in testerspec: 1462833SN/A if t < 0: 1472833SN/A print("Error: Cannot have a negative number of testers") 1482833SN/A sys.exit(1) 1495514SMichael.Adler@intel.com 1505514SMichael.Adler@intel.com for c in cachespec: 1515514SMichael.Adler@intel.com if c < 1: 1525514SMichael.Adler@intel.com print("Error: Must have 1 or more caches at each level") 1532833SN/A sys.exit(1) 1542833SN/A 1552833SN/A# Determine the tester multiplier for each level as the string 1563005Sstever@eecs.umich.edu# elements are per subsystem and it fans out 1572833SN/Amultiplier = [1] 1582833SN/Afor c in cachespec: 1592833SN/A if c < 1: 1605514SMichael.Adler@intel.com print("Error: Must have at least one cache per level") 1615514SMichael.Adler@intel.com multiplier.append(multiplier[-1] * c) 1625514SMichael.Adler@intel.com 1635514SMichael.Adler@intel.comnumtesters = 0 1642833SN/Afor t, m in zip(testerspec, multiplier): 1652833SN/A numtesters += t * m 1666642Sksewell@umich.edu 1678718Snilay@cs.wisc.edu# Define a prototype L1 cache that we scale for all successive levels 1688169SLisa.Hsu@amd.comproto_l1 = Cache(size = '32kB', assoc = 4, 1698718Snilay@cs.wisc.edu tag_latency = 1, data_latency = 1, response_latency = 1, 1708718Snilay@cs.wisc.edu tgts_per_mshr = 8) 1718169SLisa.Hsu@amd.com 1728169SLisa.Hsu@amd.comif options.blocking: 1738718Snilay@cs.wisc.edu proto_l1.mshrs = 1 1743395Shsul@eecs.umich.eduelse: 1756642Sksewell@umich.edu proto_l1.mshrs = 4 1763005Sstever@eecs.umich.edu 1773395Shsul@eecs.umich.eduif options.prefetchers: 1783395Shsul@eecs.umich.edu proto_l1.prefetcher = TaggedPrefetcher() 1793395Shsul@eecs.umich.eduelif options.stridepref: 1803323Shsul@eecs.umich.edu proto_l1.prefetcher = StridePrefetcher() 1813395Shsul@eecs.umich.edu 1823395Shsul@eecs.umich.educache_proto = [proto_l1] 1838169SLisa.Hsu@amd.com 1848169SLisa.Hsu@amd.com# Now add additional cache levels (if any) by scaling L1 params, the 1858436SBrad.Beckmann@amd.com# first element is Ln, and the last element L1 1868322Ssteve.reinhardt@amd.comfor scale in cachespec[:-1]: 1878706Sandreas.hansson@arm.com # Clone previous level and update params 1888169SLisa.Hsu@amd.com prev = cache_proto[0] 1898706Sandreas.hansson@arm.com next = prev() 1908169SLisa.Hsu@amd.com next.size = prev.size * scale 1918169SLisa.Hsu@amd.com next.tag_latency = prev.tag_latency * 10 1925056Ssaidi@eecs.umich.edu next.data_latency = prev.data_latency * 10 1933395Shsul@eecs.umich.edu next.response_latency = prev.response_latency * 10 1948167SLisa.Hsu@amd.com next.assoc = prev.assoc * scale 1953005Sstever@eecs.umich.edu next.mshrs = prev.mshrs * scale 1968169SLisa.Hsu@amd.com cache_proto.insert(0, next) 1978322Ssteve.reinhardt@amd.com 1988322Ssteve.reinhardt@amd.com# Create a config to be used by all the traffic generators 1998169SLisa.Hsu@amd.comcfg_file_name = "configs/example/memcheck.cfg" 2004968Sacolyte@umich.educfg_file = open(cfg_file_name, 'w') 2014968Sacolyte@umich.edu 2024968Sacolyte@umich.edu# Three states, with random, linear and idle behaviours. The random 2033005Sstever@eecs.umich.edu# and linear states access memory in the range [0 : 16 Mbyte] with 8 2042902SN/A# byte and 64 byte accesses respectively. 2053481Shsul@eecs.umich.educfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n") 206cfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 64 50000 150000 0\n") 207cfg_file.write("STATE 2 10000000 IDLE\n") 208cfg_file.write("INIT 0\n") 209cfg_file.write("TRANSITION 0 1 0.5\n") 210cfg_file.write("TRANSITION 0 2 0.5\n") 211cfg_file.write("TRANSITION 1 0 0.5\n") 212cfg_file.write("TRANSITION 1 2 0.5\n") 213cfg_file.write("TRANSITION 2 0 0.5\n") 214cfg_file.write("TRANSITION 2 1 0.5\n") 215cfg_file.close() 216 217# Make a prototype for the tester to be used throughout 218proto_tester = TrafficGen(config_file = cfg_file_name) 219 220# Set up the system along with a DRAM controller 221system = System(physmem = DDR3_1600_8x8()) 222 223system.voltage_domain = VoltageDomain(voltage = '1V') 224 225system.clk_domain = SrcClockDomain(clock = options.sys_clock, 226 voltage_domain = system.voltage_domain) 227 228system.memchecker = MemChecker() 229 230# For each level, track the next subsys index to use 231next_subsys_index = [0] * (len(cachespec) + 1) 232 233# Recursive function to create a sub-tree of the cache and tester 234# hierarchy 235def make_cache_level(ncaches, prototypes, level, next_cache): 236 global next_subsys_index, proto_l1, testerspec, proto_tester 237 238 index = next_subsys_index[level] 239 next_subsys_index[level] += 1 240 241 # Create a subsystem to contain the crossbar and caches, and 242 # any testers 243 subsys = SubSystem() 244 setattr(system, 'l%dsubsys%d' % (level, index), subsys) 245 246 # The levels are indexing backwards through the list 247 ntesters = testerspec[len(cachespec) - level] 248 249 testers = [proto_tester() for i in xrange(ntesters)] 250 checkers = [MemCheckerMonitor(memchecker = system.memchecker) \ 251 for i in xrange(ntesters)] 252 if ntesters: 253 subsys.tester = testers 254 subsys.checkers = checkers 255 256 if level != 0: 257 # Create a crossbar and add it to the subsystem, note that 258 # we do this even with a single element on this level 259 xbar = L2XBar(width = 32) 260 subsys.xbar = xbar 261 if next_cache: 262 xbar.master = next_cache.cpu_side 263 264 # Create and connect the caches, both the ones fanning out 265 # to create the tree, and the ones used to connect testers 266 # on this level 267 tree_caches = [prototypes[0]() for i in xrange(ncaches[0])] 268 tester_caches = [proto_l1() for i in xrange(ntesters)] 269 270 subsys.cache = tester_caches + tree_caches 271 for cache in tree_caches: 272 cache.mem_side = xbar.slave 273 make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache) 274 for tester, checker, cache in zip(testers, checkers, tester_caches): 275 tester.port = checker.slave 276 checker.master = cache.cpu_side 277 cache.mem_side = xbar.slave 278 else: 279 if not next_cache: 280 print("Error: No next-level cache at top level") 281 sys.exit(1) 282 283 if ntesters > 1: 284 # Create a crossbar and add it to the subsystem 285 xbar = L2XBar(width = 32) 286 subsys.xbar = xbar 287 xbar.master = next_cache.cpu_side 288 for tester, checker in zip(testers, checkers): 289 tester.port = checker.slave 290 checker.master = xbar.slave 291 else: 292 # Single tester 293 testers[0].port = checkers[0].slave 294 checkers[0].master = next_cache.cpu_side 295 296# Top level call to create the cache hierarchy, bottom up 297make_cache_level(cachespec, cache_proto, len(cachespec), None) 298 299# Connect the lowest level crossbar to the memory 300last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec)) 301last_subsys.xbar.master = system.physmem.port 302last_subsys.xbar.point_of_coherency = True 303 304root = Root(full_system = False, system = system) 305if options.atomic: 306 root.system.mem_mode = 'atomic' 307else: 308 root.system.mem_mode = 'timing' 309 310# The system port is never used in the tester so merely connect it 311# to avoid problems 312root.system.system_port = last_subsys.xbar.slave 313 314# Instantiate configuration 315m5.instantiate() 316 317# Simulate until program terminates 318exit_event = m5.simulate(options.maxtick) 319 320print('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) 321