fs.py revision 9665:6dbdeee787cc
112855Sgabeblack@google.com# Copyright (c) 2010-2012 ARM Limited 212855Sgabeblack@google.com# All rights reserved. 312855Sgabeblack@google.com# 412855Sgabeblack@google.com# The license below extends only to copyright in the software and shall 512855Sgabeblack@google.com# not be construed as granting a license to any other intellectual 612855Sgabeblack@google.com# property including but not limited to intellectual property relating 712855Sgabeblack@google.com# to a hardware implementation of the functionality of the software 812855Sgabeblack@google.com# licensed hereunder. You may use the software subject to the license 912855Sgabeblack@google.com# terms below provided that you ensure that this notice is replicated 1012855Sgabeblack@google.com# unmodified and in its entirety in all distributions of the software, 1112855Sgabeblack@google.com# modified or unmodified, in source code or in binary form. 1212855Sgabeblack@google.com# 1312855Sgabeblack@google.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 1412855Sgabeblack@google.com# All rights reserved. 1512855Sgabeblack@google.com# 1612855Sgabeblack@google.com# Redistribution and use in source and binary forms, with or without 1712855Sgabeblack@google.com# modification, are permitted provided that the following conditions are 1812855Sgabeblack@google.com# met: redistributions of source code must retain the above copyright 1912855Sgabeblack@google.com# notice, this list of conditions and the following disclaimer; 2012855Sgabeblack@google.com# redistributions in binary form must reproduce the above copyright 2112855Sgabeblack@google.com# notice, this list of conditions and the following disclaimer in the 2212855Sgabeblack@google.com# documentation and/or other materials provided with the distribution; 2312855Sgabeblack@google.com# neither the name of the copyright holders nor the names of its 2412855Sgabeblack@google.com# contributors may be used to endorse or promote products derived from 2512855Sgabeblack@google.com# this software without specific prior written permission. 2612855Sgabeblack@google.com# 2712855Sgabeblack@google.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2812855Sgabeblack@google.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2912855Sgabeblack@google.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3012855Sgabeblack@google.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3112855Sgabeblack@google.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3212855Sgabeblack@google.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3312855Sgabeblack@google.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3412855Sgabeblack@google.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3512855Sgabeblack@google.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3612855Sgabeblack@google.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3712855Sgabeblack@google.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3812855Sgabeblack@google.com# 3912855Sgabeblack@google.com# Authors: Ali Saidi 4012855Sgabeblack@google.com 4112855Sgabeblack@google.comimport optparse 4212855Sgabeblack@google.comimport sys 4312855Sgabeblack@google.com 4412855Sgabeblack@google.comimport m5 4512855Sgabeblack@google.comfrom m5.defines import buildEnv 4612855Sgabeblack@google.comfrom m5.objects import * 4712855Sgabeblack@google.comfrom m5.util import addToPath, fatal 4812855Sgabeblack@google.com 4912855Sgabeblack@google.comaddToPath('../common') 5012855Sgabeblack@google.com 5112855Sgabeblack@google.comfrom FSConfig import * 5212855Sgabeblack@google.comfrom SysPaths import * 5312855Sgabeblack@google.comfrom Benchmarks import * 5412855Sgabeblack@google.comimport Simulation 5512855Sgabeblack@google.comimport CacheConfig 5612855Sgabeblack@google.comfrom Caches import * 5712855Sgabeblack@google.comimport Options 5812855Sgabeblack@google.com 5912855Sgabeblack@google.comparser = optparse.OptionParser() 6012855Sgabeblack@google.comOptions.addCommonOptions(parser) 6112855Sgabeblack@google.comOptions.addFSOptions(parser) 6212855Sgabeblack@google.com 6312855Sgabeblack@google.com(options, args) = parser.parse_args() 6412855Sgabeblack@google.com 6512855Sgabeblack@google.comif args: 6612855Sgabeblack@google.com print "Error: script doesn't take any positional arguments" 6712855Sgabeblack@google.com sys.exit(1) 6812855Sgabeblack@google.com 6912855Sgabeblack@google.com# driver system CPU is always simple... note this is an assignment of 7012855Sgabeblack@google.com# a class, not an instance. 7112855Sgabeblack@google.comDriveCPUClass = AtomicSimpleCPU 7212855Sgabeblack@google.comdrive_mem_mode = 'atomic' 7312855Sgabeblack@google.com 7412855Sgabeblack@google.com# Check if KVM support has been enabled, we might need to do VM 7512855Sgabeblack@google.com# configuration if that's the case. 7612855Sgabeblack@google.comhave_kvm_support = 'BaseKvmCPU' in globals() 7712855Sgabeblack@google.comdef is_kvm_cpu(cpu_class): 7812855Sgabeblack@google.com return have_kvm_support and cpu_class != None and \ 7912855Sgabeblack@google.com issubclass(cpu_class, BaseKvmCPU) 8012855Sgabeblack@google.com 8112855Sgabeblack@google.com# system under test can be any CPU 8212855Sgabeblack@google.com(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 8312855Sgabeblack@google.com 8412855Sgabeblack@google.comTestCPUClass.clock = options.clock 85DriveCPUClass.clock = options.clock 86 87# Match the memories with the CPUs, the driver system always simple, 88# and based on the options for the test system 89DriveMemClass = SimpleMemory 90TestMemClass = Simulation.setMemClass(options) 91 92if options.benchmark: 93 try: 94 bm = Benchmarks[options.benchmark] 95 except KeyError: 96 print "Error benchmark %s has not been defined." % options.benchmark 97 print "Valid benchmarks are: %s" % DefinedBenchmarks 98 sys.exit(1) 99else: 100 if options.dual: 101 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 102 else: 103 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 104 105np = options.num_cpus 106 107if buildEnv['TARGET_ISA'] == "alpha": 108 test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0]) 109elif buildEnv['TARGET_ISA'] == "mips": 110 test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0]) 111elif buildEnv['TARGET_ISA'] == "sparc": 112 test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0]) 113elif buildEnv['TARGET_ISA'] == "x86": 114 test_sys = makeLinuxX86System(test_mem_mode, TestMemClass, 115 options.num_cpus, bm[0]) 116elif buildEnv['TARGET_ISA'] == "arm": 117 test_sys = makeArmSystem(test_mem_mode, options.machine_type, 118 TestMemClass, bm[0], options.dtb_filename, 119 bare_metal=options.bare_metal) 120else: 121 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 122 123if options.kernel is not None: 124 test_sys.kernel = binary(options.kernel) 125 126if options.script is not None: 127 test_sys.readfile = options.script 128 129test_sys.init_param = options.init_param 130 131test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 132 133if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 134 test_sys.vm = KvmVM() 135 136if options.caches or options.l2cache: 137 test_sys.iocache = IOCache(clock = '1GHz', 138 addr_ranges = test_sys.mem_ranges) 139 test_sys.iocache.cpu_side = test_sys.iobus.master 140 test_sys.iocache.mem_side = test_sys.membus.slave 141else: 142 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 143 test_sys.iobridge.slave = test_sys.iobus.master 144 test_sys.iobridge.master = test_sys.membus.slave 145 146# Sanity check 147if options.fastmem: 148 if TestCPUClass != AtomicSimpleCPU: 149 fatal("Fastmem can only be used with atomic CPU!") 150 if (options.caches or options.l2cache): 151 fatal("You cannot use fastmem in combination with caches!") 152 153for i in xrange(np): 154 if options.fastmem: 155 test_sys.cpu[i].fastmem = True 156 if options.checker: 157 test_sys.cpu[i].addCheckerCpu() 158 test_sys.cpu[i].createThreads() 159 160CacheConfig.config_cache(options, test_sys) 161 162if len(bm) == 2: 163 if buildEnv['TARGET_ISA'] == 'alpha': 164 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1]) 165 elif buildEnv['TARGET_ISA'] == 'mips': 166 drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1]) 167 elif buildEnv['TARGET_ISA'] == 'sparc': 168 drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1]) 169 elif buildEnv['TARGET_ISA'] == 'x86': 170 drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1]) 171 elif buildEnv['TARGET_ISA'] == 'arm': 172 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, 173 DriveMemClass, bm[1]) 174 175 drive_sys.cpu = DriveCPUClass(cpu_id=0) 176 drive_sys.cpu.createThreads() 177 drive_sys.cpu.createInterruptController() 178 drive_sys.cpu.connectAllPorts(drive_sys.membus) 179 if options.fastmem: 180 drive_sys.cpu.fastmem = True 181 if options.kernel is not None: 182 drive_sys.kernel = binary(options.kernel) 183 184 if is_kvm_cpu(DriveCPUClass): 185 drive_sys.vm = KvmVM() 186 187 drive_sys.iobridge = Bridge(delay='50ns', 188 ranges = drive_sys.mem_ranges) 189 drive_sys.iobridge.slave = drive_sys.iobus.master 190 drive_sys.iobridge.master = drive_sys.membus.slave 191 192 drive_sys.init_param = options.init_param 193 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 194elif len(bm) == 1: 195 root = Root(full_system=True, system=test_sys) 196else: 197 print "Error I don't know how to create more than 2 systems." 198 sys.exit(1) 199 200if options.timesync: 201 root.time_sync_enable = True 202 203if options.frame_capture: 204 VncServer.frame_capture = True 205 206Simulation.setWorkCountOptions(test_sys, options) 207Simulation.run(options, root, test_sys, FutureClass) 208