fs.py revision 9408:10a84dceab25
18012Ssaidi@eecs.umich.edu# Copyright (c) 2010-2012 ARM Limited 28029Snate@binkert.org# All rights reserved. 38029Snate@binkert.org# 48013Sbinkertn@umich.edu# The license below extends only to copyright in the software and shall 58029Snate@binkert.org# not be construed as granting a license to any other intellectual 68029Snate@binkert.org# property including but not limited to intellectual property relating 78029Snate@binkert.org# to a hardware implementation of the functionality of the software 88029Snate@binkert.org# licensed hereunder. You may use the software subject to the license 98029Snate@binkert.org# terms below provided that you ensure that this notice is replicated 108029Snate@binkert.org# unmodified and in its entirety in all distributions of the software, 118029Snate@binkert.org# modified or unmodified, in source code or in binary form. 128029Snate@binkert.org# 138029Snate@binkert.org# Copyright (c) 2006-2007 The Regents of The University of Michigan 148029Snate@binkert.org# All rights reserved. 158013Sbinkertn@umich.edu# 168029Snate@binkert.org# Redistribution and use in source and binary forms, with or without 178029Snate@binkert.org# modification, are permitted provided that the following conditions are 188029Snate@binkert.org# met: redistributions of source code must retain the above copyright 198029Snate@binkert.org# notice, this list of conditions and the following disclaimer; 208029Snate@binkert.org# redistributions in binary form must reproduce the above copyright 218029Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 228029Snate@binkert.org# documentation and/or other materials provided with the distribution; 238029Snate@binkert.org# neither the name of the copyright holders nor the names of its 248029Snate@binkert.org# contributors may be used to endorse or promote products derived from 258029Snate@binkert.org# this software without specific prior written permission. 268029Snate@binkert.org# 278013Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 288012Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 297997Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 307997Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 317997Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 327997Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 337997Ssaidi@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 347997Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 358013Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 368013Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 378013Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 388013Sbinkertn@umich.edu# 398013Sbinkertn@umich.edu# Authors: Ali Saidi 408013Sbinkertn@umich.edu 418013Sbinkertn@umich.eduimport optparse 427997Ssaidi@eecs.umich.eduimport sys 437997Ssaidi@eecs.umich.edu 447997Ssaidi@eecs.umich.eduimport m5 457997Ssaidi@eecs.umich.edufrom m5.defines import buildEnv 467997Ssaidi@eecs.umich.edufrom m5.objects import * 477997Ssaidi@eecs.umich.edufrom m5.util import addToPath, fatal 487997Ssaidi@eecs.umich.edu 497997Ssaidi@eecs.umich.eduaddToPath('../common') 507997Ssaidi@eecs.umich.edu 517997Ssaidi@eecs.umich.edufrom FSConfig import * 527997Ssaidi@eecs.umich.edufrom SysPaths import * 537997Ssaidi@eecs.umich.edufrom Benchmarks import * 547997Ssaidi@eecs.umich.eduimport Simulation 557997Ssaidi@eecs.umich.eduimport CacheConfig 567997Ssaidi@eecs.umich.edufrom Caches import * 577997Ssaidi@eecs.umich.eduimport Options 587997Ssaidi@eecs.umich.edu 597997Ssaidi@eecs.umich.eduparser = optparse.OptionParser() 607997Ssaidi@eecs.umich.eduOptions.addCommonOptions(parser) 617997Ssaidi@eecs.umich.eduOptions.addFSOptions(parser) 627997Ssaidi@eecs.umich.edu 637997Ssaidi@eecs.umich.edu(options, args) = parser.parse_args() 648013Sbinkertn@umich.edu 658013Sbinkertn@umich.eduif args: 668013Sbinkertn@umich.edu print "Error: script doesn't take any positional arguments" 678013Sbinkertn@umich.edu sys.exit(1) 688013Sbinkertn@umich.edu 698013Sbinkertn@umich.edu# driver system CPU is always simple... note this is an assignment of 708013Sbinkertn@umich.edu# a class, not an instance. 718013Sbinkertn@umich.eduDriveCPUClass = AtomicSimpleCPU 728013Sbinkertn@umich.edudrive_mem_mode = 'atomic' 738013Sbinkertn@umich.edu 748013Sbinkertn@umich.edu# system under test can be any CPU 758013Sbinkertn@umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 768013Sbinkertn@umich.edu 778013Sbinkertn@umich.eduTestCPUClass.clock = options.clock 788013Sbinkertn@umich.eduDriveCPUClass.clock = options.clock 798013Sbinkertn@umich.edu 808013Sbinkertn@umich.eduif options.benchmark: 818013Sbinkertn@umich.edu try: 828013Sbinkertn@umich.edu bm = Benchmarks[options.benchmark] 838013Sbinkertn@umich.edu except KeyError: 848013Sbinkertn@umich.edu print "Error benchmark %s has not been defined." % options.benchmark 857997Ssaidi@eecs.umich.edu print "Valid benchmarks are: %s" % DefinedBenchmarks 867997Ssaidi@eecs.umich.edu sys.exit(1) 877997Ssaidi@eecs.umich.eduelse: 887997Ssaidi@eecs.umich.edu if options.dual: 897997Ssaidi@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 907997Ssaidi@eecs.umich.edu else: 917997Ssaidi@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 927997Ssaidi@eecs.umich.edu 937997Ssaidi@eecs.umich.edunp = options.num_cpus 947997Ssaidi@eecs.umich.edu 957997Ssaidi@eecs.umich.eduif buildEnv['TARGET_ISA'] == "alpha": 967997Ssaidi@eecs.umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 977997Ssaidi@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "mips": 987997Ssaidi@eecs.umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 997997Ssaidi@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "sparc": 1007997Ssaidi@eecs.umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1017997Ssaidi@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "x86": 1027997Ssaidi@eecs.umich.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 1037997Ssaidi@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "arm": 1047997Ssaidi@eecs.umich.edu test_sys = makeArmSystem(test_mem_mode, 1057997Ssaidi@eecs.umich.edu options.machine_type, bm[0], 1067997Ssaidi@eecs.umich.edu bare_metal=options.bare_metal) 1077997Ssaidi@eecs.umich.eduelse: 1087997Ssaidi@eecs.umich.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1097997Ssaidi@eecs.umich.edu 1107997Ssaidi@eecs.umich.eduif options.kernel is not None: 1117997Ssaidi@eecs.umich.edu test_sys.kernel = binary(options.kernel) 1127997Ssaidi@eecs.umich.edu 1138013Sbinkertn@umich.eduif options.script is not None: 1148013Sbinkertn@umich.edu test_sys.readfile = options.script 1158013Sbinkertn@umich.edu 1168013Sbinkertn@umich.edutest_sys.init_param = options.init_param 1178013Sbinkertn@umich.edu 1188013Sbinkertn@umich.edutest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 1198013Sbinkertn@umich.edu 1208013Sbinkertn@umich.eduif options.caches or options.l2cache: 1218013Sbinkertn@umich.edu test_sys.iocache = IOCache(clock = '1GHz', 1228013Sbinkertn@umich.edu addr_ranges = test_sys.mem_ranges) 1237997Ssaidi@eecs.umich.edu test_sys.iocache.cpu_side = test_sys.iobus.master 1247997Ssaidi@eecs.umich.edu test_sys.iocache.mem_side = test_sys.membus.slave 1257997Ssaidi@eecs.umich.eduelse: 1267997Ssaidi@eecs.umich.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1277997Ssaidi@eecs.umich.edu test_sys.iobridge.slave = test_sys.iobus.master 1287997Ssaidi@eecs.umich.edu test_sys.iobridge.master = test_sys.membus.slave 1297997Ssaidi@eecs.umich.edu 1307997Ssaidi@eecs.umich.edu# Sanity check 1317997Ssaidi@eecs.umich.eduif options.fastmem: 1327997Ssaidi@eecs.umich.edu if TestCPUClass != AtomicSimpleCPU: 1337997Ssaidi@eecs.umich.edu fatal("Fastmem can only be used with atomic CPU!") 1347997Ssaidi@eecs.umich.edu if (options.caches or options.l2cache): 1357997Ssaidi@eecs.umich.edu fatal("You cannot use fastmem in combination with caches!") 1367997Ssaidi@eecs.umich.edu 1377997Ssaidi@eecs.umich.edufor i in xrange(np): 1387997Ssaidi@eecs.umich.edu if options.fastmem: 1397997Ssaidi@eecs.umich.edu test_sys.cpu[i].fastmem = True 1407997Ssaidi@eecs.umich.edu if options.checker: 1417997Ssaidi@eecs.umich.edu test_sys.cpu[i].addCheckerCpu() 1427997Ssaidi@eecs.umich.edu test_sys.cpu[i].createThreads() 1437997Ssaidi@eecs.umich.edu 1447997Ssaidi@eecs.umich.eduCacheConfig.config_cache(options, test_sys) 1457997Ssaidi@eecs.umich.edu 1467997Ssaidi@eecs.umich.eduif len(bm) == 2: 1477997Ssaidi@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'alpha': 1487997Ssaidi@eecs.umich.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 1497997Ssaidi@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 1507997Ssaidi@eecs.umich.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 1517997Ssaidi@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'sparc': 1527997Ssaidi@eecs.umich.edu drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 153 elif buildEnv['TARGET_ISA'] == 'x86': 154 drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 155 elif buildEnv['TARGET_ISA'] == 'arm': 156 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 157 158 drive_sys.cpu = DriveCPUClass(cpu_id=0) 159 drive_sys.cpu.createThreads() 160 drive_sys.cpu.createInterruptController() 161 drive_sys.cpu.connectAllPorts(drive_sys.membus) 162 if options.fastmem: 163 drive_sys.cpu.fastmem = True 164 if options.kernel is not None: 165 drive_sys.kernel = binary(options.kernel) 166 167 drive_sys.iobridge = Bridge(delay='50ns', 168 ranges = drive_sys.mem_ranges) 169 drive_sys.iobridge.slave = drive_sys.iobus.master 170 drive_sys.iobridge.master = drive_sys.membus.slave 171 172 drive_sys.init_param = options.init_param 173 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 174elif len(bm) == 1: 175 root = Root(full_system=True, system=test_sys) 176else: 177 print "Error I don't know how to create more than 2 systems." 178 sys.exit(1) 179 180if options.timesync: 181 root.time_sync_enable = True 182 183if options.frame_capture: 184 VncServer.frame_capture = True 185 186Simulation.setWorkCountOptions(test_sys, options) 187Simulation.run(options, root, test_sys, FutureClass) 188