fs.py revision 8870:f95c4042f2d0
110037SARM gem5 Developers# Copyright (c) 2010-2011 ARM Limited 210037SARM gem5 Developers# All rights reserved. 310037SARM gem5 Developers# 410037SARM gem5 Developers# The license below extends only to copyright in the software and shall 510037SARM gem5 Developers# not be construed as granting a license to any other intellectual 610037SARM gem5 Developers# property including but not limited to intellectual property relating 710037SARM gem5 Developers# to a hardware implementation of the functionality of the software 810037SARM gem5 Developers# licensed hereunder. You may use the software subject to the license 910037SARM gem5 Developers# terms below provided that you ensure that this notice is replicated 1010037SARM gem5 Developers# unmodified and in its entirety in all distributions of the software, 1110037SARM gem5 Developers# modified or unmodified, in source code or in binary form. 1210037SARM gem5 Developers# 1310037SARM gem5 Developers# Copyright (c) 2006-2007 The Regents of The University of Michigan 1410037SARM gem5 Developers# All rights reserved. 1510037SARM gem5 Developers# 1610037SARM gem5 Developers# Redistribution and use in source and binary forms, with or without 1710037SARM gem5 Developers# modification, are permitted provided that the following conditions are 1810037SARM gem5 Developers# met: redistributions of source code must retain the above copyright 1910037SARM gem5 Developers# notice, this list of conditions and the following disclaimer; 2010037SARM gem5 Developers# redistributions in binary form must reproduce the above copyright 2110037SARM gem5 Developers# notice, this list of conditions and the following disclaimer in the 2210037SARM gem5 Developers# documentation and/or other materials provided with the distribution; 2310037SARM gem5 Developers# neither the name of the copyright holders nor the names of its 2410037SARM gem5 Developers# contributors may be used to endorse or promote products derived from 2510037SARM gem5 Developers# this software without specific prior written permission. 2610037SARM gem5 Developers# 2710037SARM gem5 Developers# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2810037SARM gem5 Developers# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2910037SARM gem5 Developers# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3010037SARM gem5 Developers# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3110037SARM gem5 Developers# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3210037SARM gem5 Developers# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3310037SARM gem5 Developers# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3410037SARM gem5 Developers# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3510037SARM gem5 Developers# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3610037SARM gem5 Developers# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3710037SARM gem5 Developers# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3810037SARM gem5 Developers# 3910037SARM gem5 Developers# Authors: Ali Saidi 4010037SARM gem5 Developers 4110037SARM gem5 Developersimport optparse 4210037SARM gem5 Developersimport os 4310037SARM gem5 Developersimport sys 4410037SARM gem5 Developers 4510037SARM gem5 Developersimport m5 4610037SARM gem5 Developersfrom m5.defines import buildEnv 4710037SARM gem5 Developersfrom m5.objects import * 4810037SARM gem5 Developersfrom m5.util import addToPath, fatal 4910037SARM gem5 Developers 5010037SARM gem5 DevelopersaddToPath('../common') 5110037SARM gem5 Developers 5210037SARM gem5 Developersfrom FSConfig import * 5310037SARM gem5 Developersfrom SysPaths import * 5410037SARM gem5 Developersfrom Benchmarks import * 5510037SARM gem5 Developersimport Simulation 5610037SARM gem5 Developersimport CacheConfig 5710037SARM gem5 Developersfrom Caches import * 5810037SARM gem5 Developers 5910037SARM gem5 Developers# Get paths we might need. It's expected this file is in m5/configs/example. 6010037SARM gem5 Developersconfig_path = os.path.dirname(os.path.abspath(__file__)) 6110037SARM gem5 Developersconfig_root = os.path.dirname(config_path) 6210037SARM gem5 Developers 6310037SARM gem5 Developersparser = optparse.OptionParser() 6410037SARM gem5 Developers 6510037SARM gem5 Developers# Simulation options 6610037SARM gem5 Developersparser.add_option("--timesync", action="store_true", 6710037SARM gem5 Developers help="Prevent simulated time from getting ahead of real time") 6810037SARM gem5 Developers 6910037SARM gem5 Developers# System options 7010037SARM gem5 Developersparser.add_option("--kernel", action="store", type="string") 7110037SARM gem5 Developersparser.add_option("--script", action="store", type="string") 7210037SARM gem5 Developersparser.add_option("--frame-capture", action="store_true", 7310037SARM gem5 Developers help="Stores changed frame buffers from the VNC server to compressed "\ 7410037SARM gem5 Developers "files in the gem5 output directory") 7510037SARM gem5 Developers 7610037SARM gem5 Developersif buildEnv['TARGET_ISA'] == "arm": 7710037SARM gem5 Developers parser.add_option("--bare-metal", action="store_true", 7810037SARM gem5 Developers help="Provide the raw system without the linux specific bits") 7910037SARM gem5 Developers parser.add_option("--machine-type", action="store", type="choice", 8010037SARM gem5 Developers choices=ArmMachineType.map.keys(), default="RealView_PBX") 8110037SARM gem5 Developers# Benchmark options 8210037SARM gem5 Developersparser.add_option("--dual", action="store_true", 8310037SARM gem5 Developers help="Simulate two systems attached with an ethernet link") 8410037SARM gem5 Developersparser.add_option("-b", "--benchmark", action="store", type="string", 8510037SARM gem5 Developers dest="benchmark", 8610037SARM gem5 Developers help="Specify the benchmark to run. Available benchmarks: %s"\ 8710037SARM gem5 Developers % DefinedBenchmarks) 8810037SARM gem5 Developers 8910037SARM gem5 Developers# Metafile options 9010037SARM gem5 Developersparser.add_option("--etherdump", action="store", type="string", dest="etherdump", 9110037SARM gem5 Developers help="Specify the filename to dump a pcap capture of the" \ 9210037SARM gem5 Developers "ethernet traffic") 9310037SARM gem5 Developers 9410037SARM gem5 Developersexecfile(os.path.join(config_root, "common", "Options.py")) 9510037SARM gem5 Developers 9610037SARM gem5 Developers(options, args) = parser.parse_args() 9710037SARM gem5 Developers 9810037SARM gem5 Developersif args: 9910037SARM gem5 Developers print "Error: script doesn't take any positional arguments" 10010037SARM gem5 Developers sys.exit(1) 10110037SARM gem5 Developers 10210037SARM gem5 Developers# driver system CPU is always simple... note this is an assignment of 10310037SARM gem5 Developers# a class, not an instance. 10410037SARM gem5 DevelopersDriveCPUClass = AtomicSimpleCPU 10510037SARM gem5 Developersdrive_mem_mode = 'atomic' 10610037SARM gem5 Developers 10710037SARM gem5 Developers# system under test can be any CPU 10810037SARM gem5 Developers(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 109 110TestCPUClass.clock = '2GHz' 111DriveCPUClass.clock = '2GHz' 112 113if options.benchmark: 114 try: 115 bm = Benchmarks[options.benchmark] 116 except KeyError: 117 print "Error benchmark %s has not been defined." % options.benchmark 118 print "Valid benchmarks are: %s" % DefinedBenchmarks 119 sys.exit(1) 120else: 121 if options.dual: 122 bm = [SysConfig(), SysConfig()] 123 else: 124 bm = [SysConfig()] 125 126np = options.num_cpus 127 128if buildEnv['TARGET_ISA'] == "alpha": 129 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 130elif buildEnv['TARGET_ISA'] == "mips": 131 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 132elif buildEnv['TARGET_ISA'] == "sparc": 133 test_sys = makeSparcSystem(test_mem_mode, bm[0]) 134elif buildEnv['TARGET_ISA'] == "x86": 135 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 136 setWorkCountOptions(test_sys, options) 137elif buildEnv['TARGET_ISA'] == "arm": 138 test_sys = makeArmSystem(test_mem_mode, 139 options.machine_type, bm[0], 140 bare_metal=options.bare_metal) 141 setWorkCountOptions(test_sys, options) 142else: 143 fatal("incapable of building non-alpha or non-sparc full system!") 144 145if options.kernel is not None: 146 test_sys.kernel = binary(options.kernel) 147 148if options.script is not None: 149 test_sys.readfile = options.script 150 151test_sys.init_param = options.init_param 152 153test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 154 155CacheConfig.config_cache(options, test_sys) 156 157if bm[0]: 158 mem_size = bm[0].mem() 159else: 160 mem_size = SysConfig().mem() 161if options.caches or options.l2cache: 162 test_sys.iocache = IOCache(addr_range=test_sys.physmem.range) 163 test_sys.iocache.cpu_side = test_sys.iobus.master 164 test_sys.iocache.mem_side = test_sys.membus.slave 165else: 166 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', 167 ranges = [test_sys.physmem.range]) 168 test_sys.iobridge.slave = test_sys.iobus.master 169 test_sys.iobridge.master = test_sys.membus.slave 170 171for i in xrange(np): 172 if options.fastmem: 173 test_sys.cpu[i].physmem_port = test_sys.physmem.port 174 175if buildEnv['TARGET_ISA'] == 'mips': 176 setMipsOptions(TestCPUClass) 177 178if len(bm) == 2: 179 if buildEnv['TARGET_ISA'] == 'alpha': 180 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 181 elif buildEnv['TARGET_ISA'] == 'mips': 182 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 183 elif buildEnv['TARGET_ISA'] == 'sparc': 184 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 185 elif buildEnv['TARGET_ISA'] == 'x86': 186 drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 187 elif buildEnv['TARGET_ISA'] == 'arm': 188 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 189 190 drive_sys.cpu = DriveCPUClass(cpu_id=0) 191 drive_sys.cpu.createInterruptController() 192 drive_sys.cpu.connectAllPorts(drive_sys.membus) 193 if options.fastmem: 194 drive_sys.cpu.physmem_port = drive_sys.physmem.port 195 if options.kernel is not None: 196 drive_sys.kernel = binary(options.kernel) 197 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', 198 ranges = [drive_sys.physmem.range]) 199 drive_sys.iobridge.slave = drive_sys.iobus.master 200 drive_sys.iobridge.master = drive_sys.membus.slave 201 202 drive_sys.init_param = options.init_param 203 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 204elif len(bm) == 1: 205 root = Root(full_system=True, system=test_sys) 206else: 207 print "Error I don't know how to create more than 2 systems." 208 sys.exit(1) 209 210if options.timesync: 211 root.time_sync_enable = True 212 213if options.frame_capture: 214 VncServer.frame_capture = True 215 216Simulation.run(options, root, test_sys, FutureClass) 217