fs.py revision 13958:1945df12e5b0
110447Snilay@cs.wisc.edu# Copyright (c) 2010-2013, 2016, 2019 ARM Limited 210447Snilay@cs.wisc.edu# All rights reserved. 310447Snilay@cs.wisc.edu# 410447Snilay@cs.wisc.edu# The license below extends only to copyright in the software and shall 510447Snilay@cs.wisc.edu# not be construed as granting a license to any other intellectual 610447Snilay@cs.wisc.edu# property including but not limited to intellectual property relating 710447Snilay@cs.wisc.edu# to a hardware implementation of the functionality of the software 810447Snilay@cs.wisc.edu# licensed hereunder. You may use the software subject to the license 910447Snilay@cs.wisc.edu# terms below provided that you ensure that this notice is replicated 1010447Snilay@cs.wisc.edu# unmodified and in its entirety in all distributions of the software, 1110447Snilay@cs.wisc.edu# modified or unmodified, in source code or in binary form. 1210447Snilay@cs.wisc.edu# 1310447Snilay@cs.wisc.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 1410447Snilay@cs.wisc.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 1510447Snilay@cs.wisc.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 1610447Snilay@cs.wisc.edu# All rights reserved. 1710447Snilay@cs.wisc.edu# 1810447Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 1910447Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 2010447Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright 2110447Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer; 2210447Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright 2310447Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the 2410447Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution; 2510447Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its 2610447Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 2710447Snilay@cs.wisc.edu# this software without specific prior written permission. 2810447Snilay@cs.wisc.edu# 2910447Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010447Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110447Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210447Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310447Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410447Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510447Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610447Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710447Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810447Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910447Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010447Snilay@cs.wisc.edu# 4110447Snilay@cs.wisc.edu# Authors: Ali Saidi 4210447Snilay@cs.wisc.edu# Brad Beckmann 4310447Snilay@cs.wisc.edu 4410447Snilay@cs.wisc.edufrom __future__ import print_function 4510447Snilay@cs.wisc.edufrom __future__ import absolute_import 4610447Snilay@cs.wisc.edu 4710447Snilay@cs.wisc.eduimport optparse 4810447Snilay@cs.wisc.eduimport sys 4910447Snilay@cs.wisc.edu 5010447Snilay@cs.wisc.eduimport m5 5110447Snilay@cs.wisc.edufrom m5.defines import buildEnv 5210447Snilay@cs.wisc.edufrom m5.objects import * 5310447Snilay@cs.wisc.edufrom m5.util import addToPath, fatal, warn 5410447Snilay@cs.wisc.edufrom m5.util.fdthelper import * 5510447Snilay@cs.wisc.edu 5610447Snilay@cs.wisc.eduaddToPath('../') 5710447Snilay@cs.wisc.edu 5810447Snilay@cs.wisc.edufrom ruby import Ruby 5910447Snilay@cs.wisc.edu 6010447Snilay@cs.wisc.edufrom common.FSConfig import * 6110447Snilay@cs.wisc.edufrom common.SysPaths import * 6210447Snilay@cs.wisc.edufrom common.Benchmarks import * 6310447Snilay@cs.wisc.edufrom common import Simulation 6410447Snilay@cs.wisc.edufrom common import CacheConfig 6510447Snilay@cs.wisc.edufrom common import MemConfig 6610447Snilay@cs.wisc.edufrom common import CpuConfig 6710447Snilay@cs.wisc.edufrom common import BPConfig 6810447Snilay@cs.wisc.edufrom common.Caches import * 6910447Snilay@cs.wisc.edufrom common import Options 7010447Snilay@cs.wisc.edu 7110447Snilay@cs.wisc.edudef cmd_line_template(): 7210447Snilay@cs.wisc.edu if options.command_line and options.command_line_file: 7310447Snilay@cs.wisc.edu print("Error: --command-line and --command-line-file are " 7410447Snilay@cs.wisc.edu "mutually exclusive") 7510447Snilay@cs.wisc.edu sys.exit(1) 7610447Snilay@cs.wisc.edu if options.command_line: 7710447Snilay@cs.wisc.edu return options.command_line 7810447Snilay@cs.wisc.edu if options.command_line_file: 7910447Snilay@cs.wisc.edu return open(options.command_line_file).read().strip() 8010447Snilay@cs.wisc.edu return None 8110447Snilay@cs.wisc.edu 8210447Snilay@cs.wisc.edudef build_test_system(np): 8310447Snilay@cs.wisc.edu cmdline = cmd_line_template() 8410447Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "alpha": 8510447Snilay@cs.wisc.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 8610447Snilay@cs.wisc.edu cmdline=cmdline) 8710447Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "mips": 8810447Snilay@cs.wisc.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 8910447Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "sparc": 9010447Snilay@cs.wisc.edu test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 9110447Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "x86": 9210447Snilay@cs.wisc.edu test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, 9310447Snilay@cs.wisc.edu cmdline=cmdline) 9410447Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "arm": 9510447Snilay@cs.wisc.edu test_sys = makeArmSystem(test_mem_mode, options.machine_type, np, 9610447Snilay@cs.wisc.edu bm[0], options.dtb_filename, 9710447Snilay@cs.wisc.edu bare_metal=options.bare_metal, 9810447Snilay@cs.wisc.edu cmdline=cmdline, 9910447Snilay@cs.wisc.edu external_memory= 10010447Snilay@cs.wisc.edu options.external_memory_system, 10110447Snilay@cs.wisc.edu ruby=options.ruby, 10210447Snilay@cs.wisc.edu security=options.enable_security_extensions) 10310447Snilay@cs.wisc.edu if options.enable_context_switch_stats_dump: 10410447Snilay@cs.wisc.edu test_sys.enable_context_switch_stats_dump = True 10510447Snilay@cs.wisc.edu else: 10610447Snilay@cs.wisc.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 10710447Snilay@cs.wisc.edu 10810447Snilay@cs.wisc.edu # Set the cache line size for the entire system 10910447Snilay@cs.wisc.edu test_sys.cache_line_size = options.cacheline_size 11010447Snilay@cs.wisc.edu 11110447Snilay@cs.wisc.edu # Create a top-level voltage domain 11210447Snilay@cs.wisc.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 11310447Snilay@cs.wisc.edu 11410447Snilay@cs.wisc.edu # Create a source clock for the system and set the clock period 11510447Snilay@cs.wisc.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 11610447Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 11710447Snilay@cs.wisc.edu 11810447Snilay@cs.wisc.edu # Create a CPU voltage domain 11910447Snilay@cs.wisc.edu test_sys.cpu_voltage_domain = VoltageDomain() 12010447Snilay@cs.wisc.edu 12110447Snilay@cs.wisc.edu # Create a source clock for the CPUs and set the clock period 122 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 123 voltage_domain = 124 test_sys.cpu_voltage_domain) 125 126 if options.kernel is not None: 127 test_sys.kernel = binary(options.kernel) 128 else: 129 print("Error: a kernel must be provided to run in full system mode") 130 sys.exit(1) 131 132 if options.script is not None: 133 test_sys.readfile = options.script 134 135 if options.lpae: 136 test_sys.have_lpae = True 137 138 if options.virtualisation: 139 test_sys.have_virtualization = True 140 141 test_sys.init_param = options.init_param 142 143 # For now, assign all the CPUs to the same clock domain 144 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 145 for i in range(np)] 146 147 if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): 148 test_sys.kvm_vm = KvmVM() 149 150 if options.ruby: 151 bootmem = getattr(test_sys, 'bootmem', None) 152 Ruby.create_system(options, True, test_sys, test_sys.iobus, 153 test_sys._dma_ports, bootmem) 154 155 # Create a seperate clock domain for Ruby 156 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 157 voltage_domain = test_sys.voltage_domain) 158 159 # Connect the ruby io port to the PIO bus, 160 # assuming that there is just one such port. 161 test_sys.iobus.master = test_sys.ruby._io_port.slave 162 163 for (i, cpu) in enumerate(test_sys.cpu): 164 # 165 # Tie the cpu ports to the correct ruby system ports 166 # 167 cpu.clk_domain = test_sys.cpu_clk_domain 168 cpu.createThreads() 169 cpu.createInterruptController() 170 171 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 172 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 173 174 if buildEnv['TARGET_ISA'] in ("x86", "arm"): 175 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 176 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 177 178 if buildEnv['TARGET_ISA'] in "x86": 179 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 180 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 181 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 182 183 else: 184 if options.caches or options.l2cache: 185 # By default the IOCache runs at the system clock 186 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 187 test_sys.iocache.cpu_side = test_sys.iobus.master 188 test_sys.iocache.mem_side = test_sys.membus.slave 189 elif not options.external_memory_system: 190 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 191 test_sys.iobridge.slave = test_sys.iobus.master 192 test_sys.iobridge.master = test_sys.membus.slave 193 194 # Sanity check 195 if options.simpoint_profile: 196 if not CpuConfig.is_noncaching_cpu(TestCPUClass): 197 fatal("SimPoint generation should be done with atomic cpu") 198 if np > 1: 199 fatal("SimPoint generation not supported with more than one CPUs") 200 201 for i in range(np): 202 if options.simpoint_profile: 203 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 204 if options.checker: 205 test_sys.cpu[i].addCheckerCpu() 206 if options.bp_type: 207 bpClass = BPConfig.get(options.bp_type) 208 test_sys.cpu[i].branchPred = bpClass() 209 if options.indirect_bp_type: 210 IndirectBPClass = \ 211 BPConfig.get_indirect(options.indirect_bp_type) 212 test_sys.cpu[i].branchPred.indirectBranchPred = \ 213 IndirectBPClass() 214 test_sys.cpu[i].createThreads() 215 216 # If elastic tracing is enabled when not restoring from checkpoint and 217 # when not fast forwarding using the atomic cpu, then check that the 218 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 219 # passes then attach the elastic trace probe. 220 # If restoring from checkpoint or fast forwarding, the code that does this for 221 # FutureCPUClass is in the Simulation module. If the check passes then the 222 # elastic trace probe is attached to the switch CPUs. 223 if options.elastic_trace_en and options.checkpoint_restore == None and \ 224 not options.fast_forward: 225 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 226 227 CacheConfig.config_cache(options, test_sys) 228 229 MemConfig.config_mem(options, test_sys) 230 231 return test_sys 232 233def build_drive_system(np): 234 # driver system CPU is always simple, so is the memory 235 # Note this is an assignment of a class, not an instance. 236 DriveCPUClass = AtomicSimpleCPU 237 drive_mem_mode = 'atomic' 238 DriveMemClass = SimpleMemory 239 240 cmdline = cmd_line_template() 241 if buildEnv['TARGET_ISA'] == 'alpha': 242 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], 243 cmdline=cmdline) 244 elif buildEnv['TARGET_ISA'] == 'mips': 245 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 246 elif buildEnv['TARGET_ISA'] == 'sparc': 247 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 248 elif buildEnv['TARGET_ISA'] == 'x86': 249 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 250 cmdline=cmdline) 251 elif buildEnv['TARGET_ISA'] == 'arm': 252 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 253 bm[1], options.dtb_filename, cmdline=cmdline) 254 255 # Create a top-level voltage domain 256 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 257 258 # Create a source clock for the system and set the clock period 259 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 260 voltage_domain = drive_sys.voltage_domain) 261 262 # Create a CPU voltage domain 263 drive_sys.cpu_voltage_domain = VoltageDomain() 264 265 # Create a source clock for the CPUs and set the clock period 266 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 267 voltage_domain = 268 drive_sys.cpu_voltage_domain) 269 270 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 271 cpu_id=0) 272 drive_sys.cpu.createThreads() 273 drive_sys.cpu.createInterruptController() 274 drive_sys.cpu.connectAllPorts(drive_sys.membus) 275 if options.kernel is not None: 276 drive_sys.kernel = binary(options.kernel) 277 else: 278 print("Error: a kernel must be provided to run in full system mode") 279 sys.exit(1) 280 281 if CpuConfig.is_kvm_cpu(DriveCPUClass): 282 drive_sys.kvm_vm = KvmVM() 283 284 drive_sys.iobridge = Bridge(delay='50ns', 285 ranges = drive_sys.mem_ranges) 286 drive_sys.iobridge.slave = drive_sys.iobus.master 287 drive_sys.iobridge.master = drive_sys.membus.slave 288 289 # Create the appropriate memory controllers and connect them to the 290 # memory bus 291 drive_sys.mem_ctrls = [DriveMemClass(range = r) 292 for r in drive_sys.mem_ranges] 293 for i in range(len(drive_sys.mem_ctrls)): 294 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 295 296 drive_sys.init_param = options.init_param 297 298 return drive_sys 299 300# Add options 301parser = optparse.OptionParser() 302Options.addCommonOptions(parser) 303Options.addFSOptions(parser) 304 305# Add the ruby specific and protocol specific options 306if '--ruby' in sys.argv: 307 Ruby.define_options(parser) 308 309(options, args) = parser.parse_args() 310 311if args: 312 print("Error: script doesn't take any positional arguments") 313 sys.exit(1) 314 315# system under test can be any CPU 316(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 317 318# Match the memories with the CPUs, based on the options for the test system 319TestMemClass = Simulation.setMemClass(options) 320 321if options.benchmark: 322 try: 323 bm = Benchmarks[options.benchmark] 324 except KeyError: 325 print("Error benchmark %s has not been defined." % options.benchmark) 326 print("Valid benchmarks are: %s" % DefinedBenchmarks) 327 sys.exit(1) 328else: 329 if options.dual: 330 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 331 mem=options.mem_size, os_type=options.os_type), 332 SysConfig(disk=options.disk_image, rootdev=options.root_device, 333 mem=options.mem_size, os_type=options.os_type)] 334 else: 335 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 336 mem=options.mem_size, os_type=options.os_type)] 337 338np = options.num_cpus 339 340test_sys = build_test_system(np) 341if len(bm) == 2: 342 drive_sys = build_drive_system(np) 343 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 344elif len(bm) == 1 and options.dist: 345 # This system is part of a dist-gem5 simulation 346 root = makeDistRoot(test_sys, 347 options.dist_rank, 348 options.dist_size, 349 options.dist_server_name, 350 options.dist_server_port, 351 options.dist_sync_repeat, 352 options.dist_sync_start, 353 options.ethernet_linkspeed, 354 options.ethernet_linkdelay, 355 options.etherdump); 356elif len(bm) == 1: 357 root = Root(full_system=True, system=test_sys) 358else: 359 print("Error I don't know how to create more than 2 systems.") 360 sys.exit(1) 361 362if options.timesync: 363 root.time_sync_enable = True 364 365if options.frame_capture: 366 VncServer.frame_capture = True 367 368if buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \ 369 and not options.dtb_filename: 370 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]: 371 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \ 372 "platforms, unless custom hardware models have been equipped "\ 373 "with generation functionality.") 374 375 # Generate a Device Tree 376 for sysname in ('system', 'testsys', 'drivesys'): 377 if hasattr(root, sysname): 378 sys = getattr(root, sysname) 379 sys.generateDtb(m5.options.outdir, '%s.dtb' % sysname) 380 381Simulation.setWorkCountOptions(test_sys, options) 382Simulation.run(options, root, test_sys, FutureClass) 383