fs.py revision 13774
1# Copyright (c) 2010-2013, 2016, 2019 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 15# Copyright (c) 2006-2007 The Regents of The University of Michigan 16# All rights reserved. 17# 18# Redistribution and use in source and binary forms, with or without 19# modification, are permitted provided that the following conditions are 20# met: redistributions of source code must retain the above copyright 21# notice, this list of conditions and the following disclaimer; 22# redistributions in binary form must reproduce the above copyright 23# notice, this list of conditions and the following disclaimer in the 24# documentation and/or other materials provided with the distribution; 25# neither the name of the copyright holders nor the names of its 26# contributors may be used to endorse or promote products derived from 27# this software without specific prior written permission. 28# 29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40# 41# Authors: Ali Saidi 42# Brad Beckmann 43 44from __future__ import print_function 45from __future__ import absolute_import 46 47import optparse 48import sys 49 50import m5 51from m5.defines import buildEnv 52from m5.objects import * 53from m5.util import addToPath, fatal, warn 54from m5.util.fdthelper import * 55 56addToPath('../') 57 58from ruby import Ruby 59 60from common.FSConfig import * 61from common.SysPaths import * 62from common.Benchmarks import * 63from common import Simulation 64from common import CacheConfig 65from common import MemConfig 66from common import CpuConfig 67from common import BPConfig 68from common.Caches import * 69from common import Options 70 71def cmd_line_template(): 72 if options.command_line and options.command_line_file: 73 print("Error: --command-line and --command-line-file are " 74 "mutually exclusive") 75 sys.exit(1) 76 if options.command_line: 77 return options.command_line 78 if options.command_line_file: 79 return open(options.command_line_file).read().strip() 80 return None 81 82def build_test_system(np): 83 cmdline = cmd_line_template() 84 if buildEnv['TARGET_ISA'] == "alpha": 85 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 86 cmdline=cmdline) 87 elif buildEnv['TARGET_ISA'] == "mips": 88 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 89 elif buildEnv['TARGET_ISA'] == "sparc": 90 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 91 elif buildEnv['TARGET_ISA'] == "x86": 92 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 93 options.ruby, cmdline=cmdline) 94 elif buildEnv['TARGET_ISA'] == "arm": 95 test_sys = makeArmSystem(test_mem_mode, options.machine_type, 96 options.num_cpus, bm[0], options.dtb_filename, 97 bare_metal=options.bare_metal, 98 cmdline=cmdline, 99 external_memory= 100 options.external_memory_system, 101 ruby=options.ruby, 102 security=options.enable_security_extensions) 103 if options.enable_context_switch_stats_dump: 104 test_sys.enable_context_switch_stats_dump = True 105 else: 106 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 107 108 # Set the cache line size for the entire system 109 test_sys.cache_line_size = options.cacheline_size 110 111 # Create a top-level voltage domain 112 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 113 114 # Create a source clock for the system and set the clock period 115 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 116 voltage_domain = test_sys.voltage_domain) 117 118 # Create a CPU voltage domain 119 test_sys.cpu_voltage_domain = VoltageDomain() 120 121 # Create a source clock for the CPUs and set the clock period 122 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 123 voltage_domain = 124 test_sys.cpu_voltage_domain) 125 126 if options.kernel is not None: 127 test_sys.kernel = binary(options.kernel) 128 129 if options.script is not None: 130 test_sys.readfile = options.script 131 132 if options.lpae: 133 test_sys.have_lpae = True 134 135 if options.virtualisation: 136 test_sys.have_virtualization = True 137 138 test_sys.init_param = options.init_param 139 140 # For now, assign all the CPUs to the same clock domain 141 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 142 for i in range(np)] 143 144 if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): 145 test_sys.kvm_vm = KvmVM() 146 147 if options.ruby: 148 bootmem = getattr(test_sys, 'bootmem', None) 149 Ruby.create_system(options, True, test_sys, test_sys.iobus, 150 test_sys._dma_ports, bootmem) 151 152 # Create a seperate clock domain for Ruby 153 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 154 voltage_domain = test_sys.voltage_domain) 155 156 # Connect the ruby io port to the PIO bus, 157 # assuming that there is just one such port. 158 test_sys.iobus.master = test_sys.ruby._io_port.slave 159 160 for (i, cpu) in enumerate(test_sys.cpu): 161 # 162 # Tie the cpu ports to the correct ruby system ports 163 # 164 cpu.clk_domain = test_sys.cpu_clk_domain 165 cpu.createThreads() 166 cpu.createInterruptController() 167 168 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 169 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 170 171 if buildEnv['TARGET_ISA'] in ("x86", "arm"): 172 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 173 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 174 175 if buildEnv['TARGET_ISA'] in "x86": 176 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 177 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 178 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 179 180 else: 181 if options.caches or options.l2cache: 182 # By default the IOCache runs at the system clock 183 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 184 test_sys.iocache.cpu_side = test_sys.iobus.master 185 test_sys.iocache.mem_side = test_sys.membus.slave 186 elif not options.external_memory_system: 187 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 188 test_sys.iobridge.slave = test_sys.iobus.master 189 test_sys.iobridge.master = test_sys.membus.slave 190 191 # Sanity check 192 if options.simpoint_profile: 193 if not CpuConfig.is_noncaching_cpu(TestCPUClass): 194 fatal("SimPoint generation should be done with atomic cpu") 195 if np > 1: 196 fatal("SimPoint generation not supported with more than one CPUs") 197 198 for i in range(np): 199 if options.simpoint_profile: 200 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 201 if options.checker: 202 test_sys.cpu[i].addCheckerCpu() 203 if options.bp_type: 204 bpClass = BPConfig.get(options.bp_type) 205 test_sys.cpu[i].branchPred = bpClass() 206 test_sys.cpu[i].createThreads() 207 208 # If elastic tracing is enabled when not restoring from checkpoint and 209 # when not fast forwarding using the atomic cpu, then check that the 210 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 211 # passes then attach the elastic trace probe. 212 # If restoring from checkpoint or fast forwarding, the code that does this for 213 # FutureCPUClass is in the Simulation module. If the check passes then the 214 # elastic trace probe is attached to the switch CPUs. 215 if options.elastic_trace_en and options.checkpoint_restore == None and \ 216 not options.fast_forward: 217 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 218 219 CacheConfig.config_cache(options, test_sys) 220 221 MemConfig.config_mem(options, test_sys) 222 223 return test_sys 224 225def build_drive_system(np): 226 # driver system CPU is always simple, so is the memory 227 # Note this is an assignment of a class, not an instance. 228 DriveCPUClass = AtomicSimpleCPU 229 drive_mem_mode = 'atomic' 230 DriveMemClass = SimpleMemory 231 232 cmdline = cmd_line_template() 233 if buildEnv['TARGET_ISA'] == 'alpha': 234 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 235 elif buildEnv['TARGET_ISA'] == 'mips': 236 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 237 elif buildEnv['TARGET_ISA'] == 'sparc': 238 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 239 elif buildEnv['TARGET_ISA'] == 'x86': 240 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 241 cmdline=cmdline) 242 elif buildEnv['TARGET_ISA'] == 'arm': 243 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 244 bm[1], options.dtb_filename, cmdline=cmdline) 245 246 # Create a top-level voltage domain 247 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 248 249 # Create a source clock for the system and set the clock period 250 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 251 voltage_domain = drive_sys.voltage_domain) 252 253 # Create a CPU voltage domain 254 drive_sys.cpu_voltage_domain = VoltageDomain() 255 256 # Create a source clock for the CPUs and set the clock period 257 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 258 voltage_domain = 259 drive_sys.cpu_voltage_domain) 260 261 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 262 cpu_id=0) 263 drive_sys.cpu.createThreads() 264 drive_sys.cpu.createInterruptController() 265 drive_sys.cpu.connectAllPorts(drive_sys.membus) 266 if options.kernel is not None: 267 drive_sys.kernel = binary(options.kernel) 268 269 if CpuConfig.is_kvm_cpu(DriveCPUClass): 270 drive_sys.kvm_vm = KvmVM() 271 272 drive_sys.iobridge = Bridge(delay='50ns', 273 ranges = drive_sys.mem_ranges) 274 drive_sys.iobridge.slave = drive_sys.iobus.master 275 drive_sys.iobridge.master = drive_sys.membus.slave 276 277 # Create the appropriate memory controllers and connect them to the 278 # memory bus 279 drive_sys.mem_ctrls = [DriveMemClass(range = r) 280 for r in drive_sys.mem_ranges] 281 for i in range(len(drive_sys.mem_ctrls)): 282 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 283 284 drive_sys.init_param = options.init_param 285 286 return drive_sys 287 288# Add options 289parser = optparse.OptionParser() 290Options.addCommonOptions(parser) 291Options.addFSOptions(parser) 292 293# Add the ruby specific and protocol specific options 294if '--ruby' in sys.argv: 295 Ruby.define_options(parser) 296 297(options, args) = parser.parse_args() 298 299if args: 300 print("Error: script doesn't take any positional arguments") 301 sys.exit(1) 302 303# system under test can be any CPU 304(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 305 306# Match the memories with the CPUs, based on the options for the test system 307TestMemClass = Simulation.setMemClass(options) 308 309if options.benchmark: 310 try: 311 bm = Benchmarks[options.benchmark] 312 except KeyError: 313 print("Error benchmark %s has not been defined." % options.benchmark) 314 print("Valid benchmarks are: %s" % DefinedBenchmarks) 315 sys.exit(1) 316else: 317 if options.dual: 318 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 319 mem=options.mem_size, os_type=options.os_type), 320 SysConfig(disk=options.disk_image, rootdev=options.root_device, 321 mem=options.mem_size, os_type=options.os_type)] 322 else: 323 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 324 mem=options.mem_size, os_type=options.os_type)] 325 326np = options.num_cpus 327 328test_sys = build_test_system(np) 329if len(bm) == 2: 330 drive_sys = build_drive_system(np) 331 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 332elif len(bm) == 1 and options.dist: 333 # This system is part of a dist-gem5 simulation 334 root = makeDistRoot(test_sys, 335 options.dist_rank, 336 options.dist_size, 337 options.dist_server_name, 338 options.dist_server_port, 339 options.dist_sync_repeat, 340 options.dist_sync_start, 341 options.ethernet_linkspeed, 342 options.ethernet_linkdelay, 343 options.etherdump); 344elif len(bm) == 1: 345 root = Root(full_system=True, system=test_sys) 346else: 347 print("Error I don't know how to create more than 2 systems.") 348 sys.exit(1) 349 350if options.timesync: 351 root.time_sync_enable = True 352 353if options.frame_capture: 354 VncServer.frame_capture = True 355 356if buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \ 357 and not options.dtb_filename: 358 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]: 359 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \ 360 "platforms, unless custom hardware models have been equipped "\ 361 "with generation functionality.") 362 363 # Generate a Device Tree 364 for sysname in ('system', 'testsys', 'drivesys'): 365 if hasattr(root, sysname): 366 sys = getattr(root, sysname) 367 sys.generateDtb(m5.options.outdir, '%s.dtb' % sysname) 368 369Simulation.setWorkCountOptions(test_sys, options) 370Simulation.run(options, root, test_sys, FutureClass) 371