fs.py revision 13432:6ce67b7e6e44
12381SN/A# Copyright (c) 2010-2013, 2016 ARM Limited 210342SCurtis.Dunham@arm.com# All rights reserved. 38949Sandreas.hansson@arm.com# 48949Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58949Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68949Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78949Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88949Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98949Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108949Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118949Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128949Sandreas.hansson@arm.com# 138949Sandreas.hansson@arm.com# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 142592SN/A# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 157636Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 162381SN/A# All rights reserved. 172381SN/A# 182381SN/A# Redistribution and use in source and binary forms, with or without 192381SN/A# modification, are permitted provided that the following conditions are 202381SN/A# met: redistributions of source code must retain the above copyright 212381SN/A# notice, this list of conditions and the following disclaimer; 222381SN/A# redistributions in binary form must reproduce the above copyright 232381SN/A# notice, this list of conditions and the following disclaimer in the 242381SN/A# documentation and/or other materials provided with the distribution; 252381SN/A# neither the name of the copyright holders nor the names of its 262381SN/A# contributors may be used to endorse or promote products derived from 272381SN/A# this software without specific prior written permission. 282381SN/A# 292381SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302381SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312381SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322381SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332381SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342381SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352381SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362381SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372381SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382381SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392381SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu# 412665Ssaidi@eecs.umich.edu# Authors: Ali Saidi 422665Ssaidi@eecs.umich.edu# Brad Beckmann 432665Ssaidi@eecs.umich.edu 449031Sandreas.hansson@arm.comfrom __future__ import print_function 452381SN/A 462381SN/Aimport optparse 472381SN/Aimport sys 482381SN/A 492662Sstever@eecs.umich.eduimport m5 502381SN/Afrom m5.defines import buildEnv 512381SN/Afrom m5.objects import * 522381SN/Afrom m5.util import addToPath, fatal, warn 532381SN/Afrom m5.util.fdthelper import * 542381SN/A 558229Snate@binkert.orgaddToPath('../') 563348Sbinkertn@umich.edu 573348Sbinkertn@umich.edufrom ruby import Ruby 583348Sbinkertn@umich.edu 595735Snate@binkert.orgfrom common.FSConfig import * 604024Sbinkertn@umich.edufrom common.SysPaths import * 615735Snate@binkert.orgfrom common.Benchmarks import * 623940Ssaidi@eecs.umich.edufrom common import Simulation 635314Sstever@gmail.comfrom common import CacheConfig 646216Snate@binkert.orgfrom common import MemConfig 652392SN/Afrom common import CpuConfig 664167Sbinkertn@umich.edufrom common import BPConfig 672394SN/Afrom common.Caches import * 688737Skoansin.tan@gmail.comfrom common import Options 693349Sbinkertn@umich.edu 702394SN/Adef cmd_line_template(): 712812Srdreslin@umich.edu if options.command_line and options.command_line_file: 722812Srdreslin@umich.edu print("Error: --command-line and --command-line-file are " 734022Sstever@eecs.umich.edu "mutually exclusive") 744022Sstever@eecs.umich.edu sys.exit(1) 755735Snate@binkert.org if options.command_line: 765735Snate@binkert.org return options.command_line 774022Sstever@eecs.umich.edu if options.command_line_file: 785735Snate@binkert.org return open(options.command_line_file).read().strip() 795735Snate@binkert.org return None 805735Snate@binkert.org 814022Sstever@eecs.umich.edudef build_test_system(np): 824022Sstever@eecs.umich.edu cmdline = cmd_line_template() 834022Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] == "alpha": 844022Sstever@eecs.umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 854473Sstever@eecs.umich.edu cmdline=cmdline) 865319Sstever@gmail.com elif buildEnv['TARGET_ISA'] == "mips": 874022Sstever@eecs.umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 884022Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "sparc": 894022Sstever@eecs.umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 904022Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "x86": 914022Sstever@eecs.umich.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 924022Sstever@eecs.umich.edu options.ruby, cmdline=cmdline) 934022Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "arm": 949018Sandreas.hansson@arm.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, 959018Sandreas.hansson@arm.com options.num_cpus, bm[0], options.dtb_filename, 969018Sandreas.hansson@arm.com bare_metal=options.bare_metal, 979018Sandreas.hansson@arm.com cmdline=cmdline, 989018Sandreas.hansson@arm.com ignore_dtb=options.generate_dtb, 999018Sandreas.hansson@arm.com external_memory= 1009018Sandreas.hansson@arm.com options.external_memory_system, 1019018Sandreas.hansson@arm.com ruby=options.ruby, 1024022Sstever@eecs.umich.edu security=options.enable_security_extensions) 1034022Sstever@eecs.umich.edu if options.enable_context_switch_stats_dump: 1044022Sstever@eecs.umich.edu test_sys.enable_context_switch_stats_dump = True 1057465Ssteve.reinhardt@amd.com else: 1064628Sstever@eecs.umich.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1077465Ssteve.reinhardt@amd.com 1087465Ssteve.reinhardt@amd.com # Set the cache line size for the entire system 1094022Sstever@eecs.umich.edu test_sys.cache_line_size = options.cacheline_size 1104022Sstever@eecs.umich.edu 1114626Sstever@eecs.umich.edu # Create a top-level voltage domain 1124626Sstever@eecs.umich.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1137669Ssteve.reinhardt@amd.com 1144626Sstever@eecs.umich.edu # Create a source clock for the system and set the clock period 1154040Ssaidi@eecs.umich.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1164040Ssaidi@eecs.umich.edu voltage_domain = test_sys.voltage_domain) 1175650Sgblack@eecs.umich.edu 1185650Sgblack@eecs.umich.edu # Create a CPU voltage domain 1194870Sstever@eecs.umich.edu test_sys.cpu_voltage_domain = VoltageDomain() 1204870Sstever@eecs.umich.edu 1214870Sstever@eecs.umich.edu # Create a source clock for the CPUs and set the clock period 1224870Sstever@eecs.umich.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1234870Sstever@eecs.umich.edu voltage_domain = 1244870Sstever@eecs.umich.edu test_sys.cpu_voltage_domain) 1258436SBrad.Beckmann@amd.com 1268436SBrad.Beckmann@amd.com if options.kernel is not None: 1275314Sstever@gmail.com test_sys.kernel = binary(options.kernel) 1285314Sstever@gmail.com 1298184Ssomayeh@cs.wisc.edu if options.script is not None: 1308716Snilay@cs.wisc.edu test_sys.readfile = options.script 1314022Sstever@eecs.umich.edu 1324022Sstever@eecs.umich.edu if options.lpae: 1334022Sstever@eecs.umich.edu test_sys.have_lpae = True 1344022Sstever@eecs.umich.edu 1355735Snate@binkert.org if options.virtualisation: 1365735Snate@binkert.org test_sys.have_virtualization = True 1375735Snate@binkert.org 1384022Sstever@eecs.umich.edu test_sys.init_param = options.init_param 1394022Sstever@eecs.umich.edu 1404626Sstever@eecs.umich.edu # For now, assign all the CPUs to the same clock domain 1414626Sstever@eecs.umich.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1427465Ssteve.reinhardt@amd.com for i in xrange(np)] 1434022Sstever@eecs.umich.edu 1444626Sstever@eecs.umich.edu if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass): 1454626Sstever@eecs.umich.edu test_sys.kvm_vm = KvmVM() 1464626Sstever@eecs.umich.edu 1474626Sstever@eecs.umich.edu if options.ruby: 1484022Sstever@eecs.umich.edu bootmem = getattr(test_sys, 'bootmem', None) 1494022Sstever@eecs.umich.edu Ruby.create_system(options, True, test_sys, test_sys.iobus, 1506076Sgblack@eecs.umich.edu test_sys._dma_ports, bootmem) 1514626Sstever@eecs.umich.edu 1524870Sstever@eecs.umich.edu # Create a seperate clock domain for Ruby 1535314Sstever@gmail.com test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1548184Ssomayeh@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 1554022Sstever@eecs.umich.edu 1564022Sstever@eecs.umich.edu # Connect the ruby io port to the PIO bus, 1574022Sstever@eecs.umich.edu # assuming that there is just one such port. 1585735Snate@binkert.org test_sys.iobus.master = test_sys.ruby._io_port.slave 1595735Snate@binkert.org 1605735Snate@binkert.org for (i, cpu) in enumerate(test_sys.cpu): 1615735Snate@binkert.org # 1625735Snate@binkert.org # Tie the cpu ports to the correct ruby system ports 1635735Snate@binkert.org # 1645735Snate@binkert.org cpu.clk_domain = test_sys.cpu_clk_domain 1654022Sstever@eecs.umich.edu cpu.createThreads() 1665735Snate@binkert.org cpu.createInterruptController() 1675735Snate@binkert.org 1684022Sstever@eecs.umich.edu cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 1695735Snate@binkert.org cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 1704022Sstever@eecs.umich.edu 1714022Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] in ("x86", "arm"): 1724022Sstever@eecs.umich.edu cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 1735735Snate@binkert.org cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 1744022Sstever@eecs.umich.edu 1754022Sstever@eecs.umich.edu if buildEnv['TARGET_ISA'] in "x86": 1764022Sstever@eecs.umich.edu cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 1774022Sstever@eecs.umich.edu cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 1784022Sstever@eecs.umich.edu cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 1794022Sstever@eecs.umich.edu 1805735Snate@binkert.org else: 1815735Snate@binkert.org if options.caches or options.l2cache: 1825735Snate@binkert.org # By default the IOCache runs at the system clock 1834022Sstever@eecs.umich.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 1844022Sstever@eecs.umich.edu test_sys.iocache.cpu_side = test_sys.iobus.master 1854022Sstever@eecs.umich.edu test_sys.iocache.mem_side = test_sys.membus.slave 1864022Sstever@eecs.umich.edu elif not options.external_memory_system: 1874022Sstever@eecs.umich.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1884022Sstever@eecs.umich.edu test_sys.iobridge.slave = test_sys.iobus.master 1897465Ssteve.reinhardt@amd.com test_sys.iobridge.master = test_sys.membus.slave 1907465Ssteve.reinhardt@amd.com 1914022Sstever@eecs.umich.edu # Sanity check 1924022Sstever@eecs.umich.edu if options.simpoint_profile: 1934870Sstever@eecs.umich.edu if not CpuConfig.is_atomic_cpu(TestCPUClass): 1944022Sstever@eecs.umich.edu fatal("SimPoint generation should be done with atomic cpu") 1954022Sstever@eecs.umich.edu if np > 1: 1964022Sstever@eecs.umich.edu fatal("SimPoint generation not supported with more than one CPUs") 1974626Sstever@eecs.umich.edu 1986102Sgblack@eecs.umich.edu for i in xrange(np): 19910343SCurtis.Dunham@arm.com if options.simpoint_profile: 20010343SCurtis.Dunham@arm.com test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 20110343SCurtis.Dunham@arm.com if options.checker: 20210343SCurtis.Dunham@arm.com test_sys.cpu[i].addCheckerCpu() 2034870Sstever@eecs.umich.edu if options.bp_type: 2045314Sstever@gmail.com bpClass = BPConfig.get(options.bp_type) 2058184Ssomayeh@cs.wisc.edu test_sys.cpu[i].branchPred = bpClass() 2064022Sstever@eecs.umich.edu test_sys.cpu[i].createThreads() 2075735Snate@binkert.org 2085735Snate@binkert.org # If elastic tracing is enabled when not restoring from checkpoint and 2095735Snate@binkert.org # when not fast forwarding using the atomic cpu, then check that the 2104022Sstever@eecs.umich.edu # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 2114022Sstever@eecs.umich.edu # passes then attach the elastic trace probe. 2124022Sstever@eecs.umich.edu # If restoring from checkpoint or fast forwarding, the code that does this for 2135735Snate@binkert.org # FutureCPUClass is in the Simulation module. If the check passes then the 2145735Snate@binkert.org # elastic trace probe is attached to the switch CPUs. 2154022Sstever@eecs.umich.edu if options.elastic_trace_en and options.checkpoint_restore == None and \ 2164022Sstever@eecs.umich.edu not options.fast_forward: 2175735Snate@binkert.org CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 2185735Snate@binkert.org 2195735Snate@binkert.org CacheConfig.config_cache(options, test_sys) 2204022Sstever@eecs.umich.edu 2215735Snate@binkert.org MemConfig.config_mem(options, test_sys) 2225735Snate@binkert.org 2234022Sstever@eecs.umich.edu return test_sys 2244022Sstever@eecs.umich.edu 2252381SN/Adef build_drive_system(np): 2262662Sstever@eecs.umich.edu # driver system CPU is always simple, so is the memory 2272662Sstever@eecs.umich.edu # Note this is an assignment of a class, not an instance. 2282662Sstever@eecs.umich.edu DriveCPUClass = AtomicSimpleCPU 2292662Sstever@eecs.umich.edu drive_mem_mode = 'atomic' 2302662Sstever@eecs.umich.edu DriveMemClass = SimpleMemory 2312381SN/A 2329044SAli.Saidi@ARM.com cmdline = cmd_line_template() 2332381SN/A if buildEnv['TARGET_ISA'] == 'alpha': 2342813Srdreslin@umich.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2355735Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 2365735Snate@binkert.org drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2374022Sstever@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'sparc': 2385735Snate@binkert.org drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2395735Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 2405735Snate@binkert.org drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 2415735Snate@binkert.org cmdline=cmdline) 2425735Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'arm': 2435735Snate@binkert.org drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 2445735Snate@binkert.org bm[1], options.dtb_filename, cmdline=cmdline, 2455735Snate@binkert.org ignore_dtb=options.generate_dtb) 2465735Snate@binkert.org 2475735Snate@binkert.org # Create a top-level voltage domain 2485735Snate@binkert.org drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 2495735Snate@binkert.org 2505735Snate@binkert.org # Create a source clock for the system and set the clock period 2515735Snate@binkert.org drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 2525735Snate@binkert.org voltage_domain = drive_sys.voltage_domain) 2535735Snate@binkert.org 2545735Snate@binkert.org # Create a CPU voltage domain 2555735Snate@binkert.org drive_sys.cpu_voltage_domain = VoltageDomain() 2565735Snate@binkert.org 2575735Snate@binkert.org # Create a source clock for the CPUs and set the clock period 2585735Snate@binkert.org drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2595735Snate@binkert.org voltage_domain = 2605735Snate@binkert.org drive_sys.cpu_voltage_domain) 2615735Snate@binkert.org 2625735Snate@binkert.org drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2635735Snate@binkert.org cpu_id=0) 2648436SBrad.Beckmann@amd.com drive_sys.cpu.createThreads() 2658436SBrad.Beckmann@amd.com drive_sys.cpu.createInterruptController() 2668436SBrad.Beckmann@amd.com drive_sys.cpu.connectAllPorts(drive_sys.membus) 26710192Smitch.hayenga@arm.com if options.kernel is not None: 26810192Smitch.hayenga@arm.com drive_sys.kernel = binary(options.kernel) 2695735Snate@binkert.org 2705735Snate@binkert.org if CpuConfig.is_kvm_cpu(DriveCPUClass): 2715735Snate@binkert.org drive_sys.kvm_vm = KvmVM() 2725735Snate@binkert.org 2734022Sstever@eecs.umich.edu drive_sys.iobridge = Bridge(delay='50ns', 2744022Sstever@eecs.umich.edu ranges = drive_sys.mem_ranges) 2755735Snate@binkert.org drive_sys.iobridge.slave = drive_sys.iobus.master 2764870Sstever@eecs.umich.edu drive_sys.iobridge.master = drive_sys.membus.slave 2774870Sstever@eecs.umich.edu 2785735Snate@binkert.org # Create the appropriate memory controllers and connect them to the 2794870Sstever@eecs.umich.edu # memory bus 2804870Sstever@eecs.umich.edu drive_sys.mem_ctrls = [DriveMemClass(range = r) 2812566SN/A for r in drive_sys.mem_ranges] 2825735Snate@binkert.org for i in xrange(len(drive_sys.mem_ctrls)): 2835735Snate@binkert.org drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2845735Snate@binkert.org 2855735Snate@binkert.org drive_sys.init_param = options.init_param 2865735Snate@binkert.org 2875735Snate@binkert.org return drive_sys 2882566SN/A 2892566SN/A# Add options 2902566SN/Aparser = optparse.OptionParser() 2915735Snate@binkert.orgOptions.addCommonOptions(parser) 2925735Snate@binkert.orgOptions.addFSOptions(parser) 2932381SN/A 2942381SN/A# Add the ruby specific and protocol specific options 29510028SGiacomo.Gabrielli@arm.comif '--ruby' in sys.argv: 29610028SGiacomo.Gabrielli@arm.com Ruby.define_options(parser) 29710028SGiacomo.Gabrielli@arm.com 2985735Snate@binkert.org(options, args) = parser.parse_args() 2996227Snate@binkert.org 3002381SN/Aif args: 3015735Snate@binkert.org print("Error: script doesn't take any positional arguments") 3029030Sandreas.hansson@arm.com sys.exit(1) 3039030Sandreas.hansson@arm.com 3049030Sandreas.hansson@arm.com# system under test can be any CPU 3059030Sandreas.hansson@arm.com(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 3069030Sandreas.hansson@arm.com 3079030Sandreas.hansson@arm.com# Match the memories with the CPUs, based on the options for the test system 3089030Sandreas.hansson@arm.comTestMemClass = Simulation.setMemClass(options) 3099030Sandreas.hansson@arm.com 3109030Sandreas.hansson@arm.comif options.benchmark: 3119030Sandreas.hansson@arm.com try: 3125735Snate@binkert.org bm = Benchmarks[options.benchmark] 3139031Sandreas.hansson@arm.com except KeyError: 3142381SN/A print("Error benchmark %s has not been defined." % options.benchmark) 3155735Snate@binkert.org print("Valid benchmarks are: %s" % DefinedBenchmarks) 3169030Sandreas.hansson@arm.com sys.exit(1) 3179030Sandreas.hansson@arm.comelse: 3189030Sandreas.hansson@arm.com if options.dual: 3199030Sandreas.hansson@arm.com bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 3209030Sandreas.hansson@arm.com mem=options.mem_size, os_type=options.os_type), 3219030Sandreas.hansson@arm.com SysConfig(disk=options.disk_image, rootdev=options.root_device, 3225735Snate@binkert.org mem=options.mem_size, os_type=options.os_type)] 3239031Sandreas.hansson@arm.com else: 3242641Sstever@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 3255735Snate@binkert.org mem=options.mem_size, os_type=options.os_type)] 3265735Snate@binkert.org 3274870Sstever@eecs.umich.edunp = options.num_cpus 3284870Sstever@eecs.umich.edu 3294870Sstever@eecs.umich.edutest_sys = build_test_system(np) 3304870Sstever@eecs.umich.eduif len(bm) == 2: 3314870Sstever@eecs.umich.edu drive_sys = build_drive_system(np) 3324870Sstever@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 3338668Sgeoffrey.blake@arm.comelif len(bm) == 1 and options.dist: 3348668Sgeoffrey.blake@arm.com # This system is part of a dist-gem5 simulation 3358668Sgeoffrey.blake@arm.com root = makeDistRoot(test_sys, 3368668Sgeoffrey.blake@arm.com options.dist_rank, 3378668Sgeoffrey.blake@arm.com options.dist_size, 3388668Sgeoffrey.blake@arm.com options.dist_server_name, 3398668Sgeoffrey.blake@arm.com options.dist_server_port, 3402641Sstever@eecs.umich.edu options.dist_sync_repeat, 3412811Srdreslin@umich.edu options.dist_sync_start, 3429547Sandreas.hansson@arm.com options.ethernet_linkspeed, 3439547Sandreas.hansson@arm.com options.ethernet_linkdelay, 3449547Sandreas.hansson@arm.com options.etherdump); 3459547Sandreas.hansson@arm.comelif len(bm) == 1: 3469547Sandreas.hansson@arm.com root = Root(full_system=True, system=test_sys) 3479547Sandreas.hansson@arm.comelse: 3489547Sandreas.hansson@arm.com print("Error I don't know how to create more than 2 systems.") 3499547Sandreas.hansson@arm.com sys.exit(1) 3503218Sgblack@eecs.umich.edu 3519547Sandreas.hansson@arm.comif options.timesync: 3529547Sandreas.hansson@arm.com root.time_sync_enable = True 3539547Sandreas.hansson@arm.com 3549547Sandreas.hansson@arm.comif options.frame_capture: 3559547Sandreas.hansson@arm.com VncServer.frame_capture = True 3569547Sandreas.hansson@arm.com 3579547Sandreas.hansson@arm.comif buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb: 3589547Sandreas.hansson@arm.com # Sanity checks 3593218Sgblack@eecs.umich.edu if options.dtb_filename: 3605735Snate@binkert.org fatal("--generate-dtb and --dtb-filename cannot be specified at the"\ 3615735Snate@binkert.org "same time.") 3629542Sandreas.hansson@arm.com 3639542Sandreas.hansson@arm.com if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]: 3649542Sandreas.hansson@arm.com warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \ 3659542Sandreas.hansson@arm.com "platforms, unless custom hardware models have been equipped "\ 3669542Sandreas.hansson@arm.com "with generation functionality.") 3679542Sandreas.hansson@arm.com 3689542Sandreas.hansson@arm.com # Generate a Device Tree 3699542Sandreas.hansson@arm.com def create_dtb_for_system(system, filename): 3709542Sandreas.hansson@arm.com state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1) 3719542Sandreas.hansson@arm.com rootNode = system.generateDeviceTree(state) 3729542Sandreas.hansson@arm.com 3739542Sandreas.hansson@arm.com fdt = Fdt() 3749542Sandreas.hansson@arm.com fdt.add_rootnode(rootNode) 3759542Sandreas.hansson@arm.com dtb_filename = os.path.join(m5.options.outdir, filename) 3765735Snate@binkert.org return fdt.writeDtbFile(dtb_filename) 3775735Snate@binkert.org 3785735Snate@binkert.org for sysname in ('system', 'testsys', 'drivesys'): 3799542Sandreas.hansson@arm.com if hasattr(root, sysname): 3809542Sandreas.hansson@arm.com sys = getattr(root, sysname) 3812641Sstever@eecs.umich.edu sys.dtb_filename = create_dtb_for_system(sys, '%s.dtb' % sysname) 3822641Sstever@eecs.umich.edu 3832641Sstever@eecs.umich.eduSimulation.setWorkCountOptions(test_sys, options) 3845315Sstever@gmail.comSimulation.run(options, root, test_sys, FutureClass) 3855315Sstever@gmail.com