fs.py revision 12598:b80b2d9a251b 
1# Copyright (c) 2010-2013, 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42#          Brad Beckmann
43
44from __future__ import print_function
45
46import optparse
47import sys
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal, warn
53from m5.util.fdthelper import *
54
55addToPath('../')
56
57from ruby import Ruby
58
59from common.FSConfig import *
60from common.SysPaths import *
61from common.Benchmarks import *
62from common import Simulation
63from common import CacheConfig
64from common import MemConfig
65from common import CpuConfig
66from common.Caches import *
67from common import Options
68
69
70# Check if KVM support has been enabled, we might need to do VM
71# configuration if that's the case.
72have_kvm_support = 'BaseKvmCPU' in globals()
73def is_kvm_cpu(cpu_class):
74    return have_kvm_support and cpu_class != None and \
75        issubclass(cpu_class, BaseKvmCPU)
76
77def cmd_line_template():
78    if options.command_line and options.command_line_file:
79        print("Error: --command-line and --command-line-file are "
80              "mutually exclusive")
81        sys.exit(1)
82    if options.command_line:
83        return options.command_line
84    if options.command_line_file:
85        return open(options.command_line_file).read().strip()
86    return None
87
88def build_test_system(np):
89    cmdline = cmd_line_template()
90    if buildEnv['TARGET_ISA'] == "alpha":
91        test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
92                                        cmdline=cmdline)
93    elif buildEnv['TARGET_ISA'] == "mips":
94        test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
95    elif buildEnv['TARGET_ISA'] == "sparc":
96        test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
97    elif buildEnv['TARGET_ISA'] == "x86":
98        test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
99                options.ruby, cmdline=cmdline)
100    elif buildEnv['TARGET_ISA'] == "arm":
101        test_sys = makeArmSystem(test_mem_mode, options.machine_type,
102                                 options.num_cpus, bm[0], options.dtb_filename,
103                                 bare_metal=options.bare_metal,
104                                 cmdline=cmdline,
105                                 ignore_dtb=options.generate_dtb,
106                                 external_memory=
107                                   options.external_memory_system,
108                                 ruby=options.ruby,
109                                 security=options.enable_security_extensions)
110        if options.enable_context_switch_stats_dump:
111            test_sys.enable_context_switch_stats_dump = True
112    else:
113        fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
114
115    # Set the cache line size for the entire system
116    test_sys.cache_line_size = options.cacheline_size
117
118    # Create a top-level voltage domain
119    test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
120
121    # Create a source clock for the system and set the clock period
122    test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
123            voltage_domain = test_sys.voltage_domain)
124
125    # Create a CPU voltage domain
126    test_sys.cpu_voltage_domain = VoltageDomain()
127
128    # Create a source clock for the CPUs and set the clock period
129    test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
130                                             voltage_domain =
131                                             test_sys.cpu_voltage_domain)
132
133    if options.kernel is not None:
134        test_sys.kernel = binary(options.kernel)
135
136    if options.script is not None:
137        test_sys.readfile = options.script
138
139    if options.lpae:
140        test_sys.have_lpae = True
141
142    if options.virtualisation:
143        test_sys.have_virtualization = True
144
145    test_sys.init_param = options.init_param
146
147    # For now, assign all the CPUs to the same clock domain
148    test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
149                    for i in xrange(np)]
150
151    if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
152        test_sys.kvm_vm = KvmVM()
153
154    if options.ruby:
155        bootmem = getattr(test_sys, 'bootmem', None)
156        Ruby.create_system(options, True, test_sys, test_sys.iobus,
157                           test_sys._dma_ports, bootmem)
158
159        # Create a seperate clock domain for Ruby
160        test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
161                                        voltage_domain = test_sys.voltage_domain)
162
163        # Connect the ruby io port to the PIO bus,
164        # assuming that there is just one such port.
165        test_sys.iobus.master = test_sys.ruby._io_port.slave
166
167        for (i, cpu) in enumerate(test_sys.cpu):
168            #
169            # Tie the cpu ports to the correct ruby system ports
170            #
171            cpu.clk_domain = test_sys.cpu_clk_domain
172            cpu.createThreads()
173            cpu.createInterruptController()
174
175            cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
176            cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
177
178            if buildEnv['TARGET_ISA'] in ("x86", "arm"):
179                cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
180                cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
181
182            if buildEnv['TARGET_ISA'] in "x86":
183                cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
184                cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
185                cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
186
187    else:
188        if options.caches or options.l2cache:
189            # By default the IOCache runs at the system clock
190            test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
191            test_sys.iocache.cpu_side = test_sys.iobus.master
192            test_sys.iocache.mem_side = test_sys.membus.slave
193        elif not options.external_memory_system:
194            test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
195            test_sys.iobridge.slave = test_sys.iobus.master
196            test_sys.iobridge.master = test_sys.membus.slave
197
198        # Sanity check
199        if options.fastmem:
200            if TestCPUClass != AtomicSimpleCPU:
201                fatal("Fastmem can only be used with atomic CPU!")
202            if (options.caches or options.l2cache):
203                fatal("You cannot use fastmem in combination with caches!")
204
205        if options.simpoint_profile:
206            if not options.fastmem:
207                # Atomic CPU checked with fastmem option already
208                fatal("SimPoint generation should be done with atomic cpu and fastmem")
209            if np > 1:
210                fatal("SimPoint generation not supported with more than one CPUs")
211
212        for i in xrange(np):
213            if options.fastmem:
214                test_sys.cpu[i].fastmem = True
215            if options.simpoint_profile:
216                test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
217            if options.checker:
218                test_sys.cpu[i].addCheckerCpu()
219            test_sys.cpu[i].createThreads()
220
221        # If elastic tracing is enabled when not restoring from checkpoint and
222        # when not fast forwarding using the atomic cpu, then check that the
223        # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
224        # passes then attach the elastic trace probe.
225        # If restoring from checkpoint or fast forwarding, the code that does this for
226        # FutureCPUClass is in the Simulation module. If the check passes then the
227        # elastic trace probe is attached to the switch CPUs.
228        if options.elastic_trace_en and options.checkpoint_restore == None and \
229            not options.fast_forward:
230            CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
231
232        CacheConfig.config_cache(options, test_sys)
233
234        MemConfig.config_mem(options, test_sys)
235
236    return test_sys
237
238def build_drive_system(np):
239    # driver system CPU is always simple, so is the memory
240    # Note this is an assignment of a class, not an instance.
241    DriveCPUClass = AtomicSimpleCPU
242    drive_mem_mode = 'atomic'
243    DriveMemClass = SimpleMemory
244
245    cmdline = cmd_line_template()
246    if buildEnv['TARGET_ISA'] == 'alpha':
247        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline)
248    elif buildEnv['TARGET_ISA'] == 'mips':
249        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
250    elif buildEnv['TARGET_ISA'] == 'sparc':
251        drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
252    elif buildEnv['TARGET_ISA'] == 'x86':
253        drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
254                                       cmdline=cmdline)
255    elif buildEnv['TARGET_ISA'] == 'arm':
256        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
257                                  bm[1], options.dtb_filename, cmdline=cmdline,
258                                  ignore_dtb=options.generate_dtb)
259
260    # Create a top-level voltage domain
261    drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
262
263    # Create a source clock for the system and set the clock period
264    drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
265            voltage_domain = drive_sys.voltage_domain)
266
267    # Create a CPU voltage domain
268    drive_sys.cpu_voltage_domain = VoltageDomain()
269
270    # Create a source clock for the CPUs and set the clock period
271    drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
272                                              voltage_domain =
273                                              drive_sys.cpu_voltage_domain)
274
275    drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
276                                  cpu_id=0)
277    drive_sys.cpu.createThreads()
278    drive_sys.cpu.createInterruptController()
279    drive_sys.cpu.connectAllPorts(drive_sys.membus)
280    if options.fastmem:
281        drive_sys.cpu.fastmem = True
282    if options.kernel is not None:
283        drive_sys.kernel = binary(options.kernel)
284
285    if is_kvm_cpu(DriveCPUClass):
286        drive_sys.kvm_vm = KvmVM()
287
288    drive_sys.iobridge = Bridge(delay='50ns',
289                                ranges = drive_sys.mem_ranges)
290    drive_sys.iobridge.slave = drive_sys.iobus.master
291    drive_sys.iobridge.master = drive_sys.membus.slave
292
293    # Create the appropriate memory controllers and connect them to the
294    # memory bus
295    drive_sys.mem_ctrls = [DriveMemClass(range = r)
296                           for r in drive_sys.mem_ranges]
297    for i in xrange(len(drive_sys.mem_ctrls)):
298        drive_sys.mem_ctrls[i].port = drive_sys.membus.master
299
300    drive_sys.init_param = options.init_param
301
302    return drive_sys
303
304# Add options
305parser = optparse.OptionParser()
306Options.addCommonOptions(parser)
307Options.addFSOptions(parser)
308
309# Add the ruby specific and protocol specific options
310if '--ruby' in sys.argv:
311    Ruby.define_options(parser)
312
313(options, args) = parser.parse_args()
314
315if args:
316    print("Error: script doesn't take any positional arguments")
317    sys.exit(1)
318
319# system under test can be any CPU
320(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
321
322# Match the memories with the CPUs, based on the options for the test system
323TestMemClass = Simulation.setMemClass(options)
324
325if options.benchmark:
326    try:
327        bm = Benchmarks[options.benchmark]
328    except KeyError:
329        print("Error benchmark %s has not been defined." % options.benchmark)
330        print("Valid benchmarks are: %s" % DefinedBenchmarks)
331        sys.exit(1)
332else:
333    if options.dual:
334        bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
335                        mem=options.mem_size, os_type=options.os_type),
336              SysConfig(disk=options.disk_image, rootdev=options.root_device,
337                        mem=options.mem_size, os_type=options.os_type)]
338    else:
339        bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
340                        mem=options.mem_size, os_type=options.os_type)]
341
342np = options.num_cpus
343
344test_sys = build_test_system(np)
345if len(bm) == 2:
346    drive_sys = build_drive_system(np)
347    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
348elif len(bm) == 1 and options.dist:
349    # This system is part of a dist-gem5 simulation
350    root = makeDistRoot(test_sys,
351                        options.dist_rank,
352                        options.dist_size,
353                        options.dist_server_name,
354                        options.dist_server_port,
355                        options.dist_sync_repeat,
356                        options.dist_sync_start,
357                        options.ethernet_linkspeed,
358                        options.ethernet_linkdelay,
359                        options.etherdump);
360elif len(bm) == 1:
361    root = Root(full_system=True, system=test_sys)
362else:
363    print("Error I don't know how to create more than 2 systems.")
364    sys.exit(1)
365
366if options.timesync:
367    root.time_sync_enable = True
368
369if options.frame_capture:
370    VncServer.frame_capture = True
371
372if buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb:
373    # Sanity checks
374    if options.dtb_filename:
375        fatal("--generate-dtb and --dtb-filename cannot be specified at the"\
376             "same time.")
377
378    if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
379        warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
380             "platforms, unless custom hardware models have been equipped "\
381             "with generation functionality.")
382
383    # Generate a Device Tree
384    def create_dtb_for_system(system, filename):
385        state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
386        rootNode = system.generateDeviceTree(state)
387
388        fdt = Fdt()
389        fdt.add_rootnode(rootNode)
390        dtb_filename = os.path.join(m5.options.outdir, filename)
391        return fdt.writeDtbFile(dtb_filename)
392
393    for sysname in ('system', 'testsys', 'drivesys'):
394        if hasattr(root, sysname):
395            sys = getattr(root, sysname)
396            sys.dtb_filename = create_dtb_for_system(sys, '%s.dtb' % sysname)
397
398Simulation.setWorkCountOptions(test_sys, options)
399Simulation.run(options, root, test_sys, FutureClass)
400