fs.py revision 12564:2778478ca882
18012Ssaidi@eecs.umich.edu# Copyright (c) 2010-2013, 2016 ARM Limited 28029Snate@binkert.org# All rights reserved. 38029Snate@binkert.org# 48013Sbinkertn@umich.edu# The license below extends only to copyright in the software and shall 58029Snate@binkert.org# not be construed as granting a license to any other intellectual 68029Snate@binkert.org# property including but not limited to intellectual property relating 78029Snate@binkert.org# to a hardware implementation of the functionality of the software 88029Snate@binkert.org# licensed hereunder. You may use the software subject to the license 98029Snate@binkert.org# terms below provided that you ensure that this notice is replicated 108029Snate@binkert.org# unmodified and in its entirety in all distributions of the software, 118029Snate@binkert.org# modified or unmodified, in source code or in binary form. 128029Snate@binkert.org# 138029Snate@binkert.org# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 148029Snate@binkert.org# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 158013Sbinkertn@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 168029Snate@binkert.org# All rights reserved. 178029Snate@binkert.org# 188029Snate@binkert.org# Redistribution and use in source and binary forms, with or without 198029Snate@binkert.org# modification, are permitted provided that the following conditions are 208029Snate@binkert.org# met: redistributions of source code must retain the above copyright 218029Snate@binkert.org# notice, this list of conditions and the following disclaimer; 228029Snate@binkert.org# redistributions in binary form must reproduce the above copyright 238029Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 248029Snate@binkert.org# documentation and/or other materials provided with the distribution; 258029Snate@binkert.org# neither the name of the copyright holders nor the names of its 268029Snate@binkert.org# contributors may be used to endorse or promote products derived from 278013Sbinkertn@umich.edu# this software without specific prior written permission. 288012Ssaidi@eecs.umich.edu# 297997Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307997Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317997Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327997Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337997Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347997Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 358013Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 368013Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377997Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387997Ssaidi@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 398013Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 408013Sbinkertn@umich.edu# 417997Ssaidi@eecs.umich.edu# Authors: Ali Saidi 427997Ssaidi@eecs.umich.edu# Brad Beckmann 437997Ssaidi@eecs.umich.edu 447997Ssaidi@eecs.umich.edufrom __future__ import print_function 457997Ssaidi@eecs.umich.edu 467997Ssaidi@eecs.umich.eduimport optparse 477997Ssaidi@eecs.umich.eduimport sys 487997Ssaidi@eecs.umich.edu 497997Ssaidi@eecs.umich.eduimport m5 507997Ssaidi@eecs.umich.edufrom m5.defines import buildEnv 517997Ssaidi@eecs.umich.edufrom m5.objects import * 527997Ssaidi@eecs.umich.edufrom m5.util import addToPath, fatal, warn 537997Ssaidi@eecs.umich.edufrom m5.util.fdthelper import * 547997Ssaidi@eecs.umich.edu 557997Ssaidi@eecs.umich.eduaddToPath('../') 567997Ssaidi@eecs.umich.edu 577997Ssaidi@eecs.umich.edufrom ruby import Ruby 587997Ssaidi@eecs.umich.edu 597997Ssaidi@eecs.umich.edufrom common.FSConfig import * 607997Ssaidi@eecs.umich.edufrom common.SysPaths import * 617997Ssaidi@eecs.umich.edufrom common.Benchmarks import * 627997Ssaidi@eecs.umich.edufrom common import Simulation 637997Ssaidi@eecs.umich.edufrom common import CacheConfig 647997Ssaidi@eecs.umich.edufrom common import MemConfig 657997Ssaidi@eecs.umich.edufrom common import CpuConfig 667997Ssaidi@eecs.umich.edufrom common.Caches import * 677997Ssaidi@eecs.umich.edufrom common import Options 687997Ssaidi@eecs.umich.edu 697997Ssaidi@eecs.umich.edu 707997Ssaidi@eecs.umich.edu# Check if KVM support has been enabled, we might need to do VM 717997Ssaidi@eecs.umich.edu# configuration if that's the case. 727997Ssaidi@eecs.umich.eduhave_kvm_support = 'BaseKvmCPU' in globals() 737997Ssaidi@eecs.umich.edudef is_kvm_cpu(cpu_class): 747997Ssaidi@eecs.umich.edu return have_kvm_support and cpu_class != None and \ 757997Ssaidi@eecs.umich.edu issubclass(cpu_class, BaseKvmCPU) 767997Ssaidi@eecs.umich.edu 777997Ssaidi@eecs.umich.edudef cmd_line_template(): 787997Ssaidi@eecs.umich.edu if options.command_line and options.command_line_file: 797997Ssaidi@eecs.umich.edu print("Error: --command-line and --command-line-file are " 807997Ssaidi@eecs.umich.edu "mutually exclusive") 817997Ssaidi@eecs.umich.edu sys.exit(1) 827997Ssaidi@eecs.umich.edu if options.command_line: 837997Ssaidi@eecs.umich.edu return options.command_line 847997Ssaidi@eecs.umich.edu if options.command_line_file: 857997Ssaidi@eecs.umich.edu return open(options.command_line_file).read().strip() 867997Ssaidi@eecs.umich.edu return None 877997Ssaidi@eecs.umich.edu 887997Ssaidi@eecs.umich.edudef build_test_system(np): 897997Ssaidi@eecs.umich.edu cmdline = cmd_line_template() 907997Ssaidi@eecs.umich.edu if buildEnv['TARGET_ISA'] == "alpha": 917997Ssaidi@eecs.umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 927997Ssaidi@eecs.umich.edu cmdline=cmdline) 937997Ssaidi@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "mips": 947997Ssaidi@eecs.umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 957997Ssaidi@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "sparc": 967997Ssaidi@eecs.umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 977997Ssaidi@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "x86": 987997Ssaidi@eecs.umich.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 997997Ssaidi@eecs.umich.edu options.ruby, cmdline=cmdline) 1007997Ssaidi@eecs.umich.edu elif buildEnv['TARGET_ISA'] == "arm": 1017997Ssaidi@eecs.umich.edu test_sys = makeArmSystem(test_mem_mode, options.machine_type, 1027997Ssaidi@eecs.umich.edu options.num_cpus, bm[0], options.dtb_filename, 1037997Ssaidi@eecs.umich.edu bare_metal=options.bare_metal, 1047997Ssaidi@eecs.umich.edu cmdline=cmdline, 1057997Ssaidi@eecs.umich.edu ignore_dtb=options.generate_dtb, 1067997Ssaidi@eecs.umich.edu external_memory= 1077997Ssaidi@eecs.umich.edu options.external_memory_system, 1087997Ssaidi@eecs.umich.edu ruby=options.ruby, 1097997Ssaidi@eecs.umich.edu security=options.enable_security_extensions) 1107997Ssaidi@eecs.umich.edu if options.enable_context_switch_stats_dump: 1117997Ssaidi@eecs.umich.edu test_sys.enable_context_switch_stats_dump = True 1127997Ssaidi@eecs.umich.edu else: 1137997Ssaidi@eecs.umich.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1147997Ssaidi@eecs.umich.edu 1157997Ssaidi@eecs.umich.edu # Set the cache line size for the entire system 1167997Ssaidi@eecs.umich.edu test_sys.cache_line_size = options.cacheline_size 1177997Ssaidi@eecs.umich.edu 1187997Ssaidi@eecs.umich.edu # Create a top-level voltage domain 1197997Ssaidi@eecs.umich.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1207997Ssaidi@eecs.umich.edu 1217997Ssaidi@eecs.umich.edu # Create a source clock for the system and set the clock period 1227997Ssaidi@eecs.umich.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1237997Ssaidi@eecs.umich.edu voltage_domain = test_sys.voltage_domain) 1247997Ssaidi@eecs.umich.edu 1257997Ssaidi@eecs.umich.edu # Create a CPU voltage domain 1267997Ssaidi@eecs.umich.edu test_sys.cpu_voltage_domain = VoltageDomain() 1277997Ssaidi@eecs.umich.edu 1287997Ssaidi@eecs.umich.edu # Create a source clock for the CPUs and set the clock period 1297997Ssaidi@eecs.umich.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1307997Ssaidi@eecs.umich.edu voltage_domain = 1317997Ssaidi@eecs.umich.edu test_sys.cpu_voltage_domain) 1327997Ssaidi@eecs.umich.edu 1337997Ssaidi@eecs.umich.edu if options.kernel is not None: 1347997Ssaidi@eecs.umich.edu test_sys.kernel = binary(options.kernel) 1357997Ssaidi@eecs.umich.edu 1367997Ssaidi@eecs.umich.edu if options.script is not None: 1377997Ssaidi@eecs.umich.edu test_sys.readfile = options.script 1387997Ssaidi@eecs.umich.edu 1397997Ssaidi@eecs.umich.edu if options.lpae: 1407997Ssaidi@eecs.umich.edu test_sys.have_lpae = True 1417997Ssaidi@eecs.umich.edu 1427997Ssaidi@eecs.umich.edu if options.virtualisation: 1437997Ssaidi@eecs.umich.edu test_sys.have_virtualization = True 1447997Ssaidi@eecs.umich.edu 1457997Ssaidi@eecs.umich.edu test_sys.init_param = options.init_param 1467997Ssaidi@eecs.umich.edu 1477997Ssaidi@eecs.umich.edu # For now, assign all the CPUs to the same clock domain 1487997Ssaidi@eecs.umich.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1497997Ssaidi@eecs.umich.edu for i in xrange(np)] 1507997Ssaidi@eecs.umich.edu 1517997Ssaidi@eecs.umich.edu if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1527997Ssaidi@eecs.umich.edu test_sys.kvm_vm = KvmVM() 1537997Ssaidi@eecs.umich.edu 1547997Ssaidi@eecs.umich.edu if options.ruby: 1557997Ssaidi@eecs.umich.edu Ruby.create_system(options, True, test_sys, test_sys.iobus, 1567997Ssaidi@eecs.umich.edu test_sys._dma_ports) 1577997Ssaidi@eecs.umich.edu 1587997Ssaidi@eecs.umich.edu # Create a seperate clock domain for Ruby 1597997Ssaidi@eecs.umich.edu test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1607997Ssaidi@eecs.umich.edu voltage_domain = test_sys.voltage_domain) 1617997Ssaidi@eecs.umich.edu 1627997Ssaidi@eecs.umich.edu # Connect the ruby io port to the PIO bus, 163 # assuming that there is just one such port. 164 test_sys.iobus.master = test_sys.ruby._io_port.slave 165 166 for (i, cpu) in enumerate(test_sys.cpu): 167 # 168 # Tie the cpu ports to the correct ruby system ports 169 # 170 cpu.clk_domain = test_sys.cpu_clk_domain 171 cpu.createThreads() 172 cpu.createInterruptController() 173 174 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 175 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 176 177 if buildEnv['TARGET_ISA'] in ("x86", "arm"): 178 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 179 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 180 181 if buildEnv['TARGET_ISA'] in "x86": 182 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 183 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 184 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 185 186 else: 187 if options.caches or options.l2cache: 188 # By default the IOCache runs at the system clock 189 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 190 test_sys.iocache.cpu_side = test_sys.iobus.master 191 test_sys.iocache.mem_side = test_sys.membus.slave 192 elif not options.external_memory_system: 193 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 194 test_sys.iobridge.slave = test_sys.iobus.master 195 test_sys.iobridge.master = test_sys.membus.slave 196 197 # Sanity check 198 if options.fastmem: 199 if TestCPUClass != AtomicSimpleCPU: 200 fatal("Fastmem can only be used with atomic CPU!") 201 if (options.caches or options.l2cache): 202 fatal("You cannot use fastmem in combination with caches!") 203 204 if options.simpoint_profile: 205 if not options.fastmem: 206 # Atomic CPU checked with fastmem option already 207 fatal("SimPoint generation should be done with atomic cpu and fastmem") 208 if np > 1: 209 fatal("SimPoint generation not supported with more than one CPUs") 210 211 for i in xrange(np): 212 if options.fastmem: 213 test_sys.cpu[i].fastmem = True 214 if options.simpoint_profile: 215 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 216 if options.checker: 217 test_sys.cpu[i].addCheckerCpu() 218 test_sys.cpu[i].createThreads() 219 220 # If elastic tracing is enabled when not restoring from checkpoint and 221 # when not fast forwarding using the atomic cpu, then check that the 222 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 223 # passes then attach the elastic trace probe. 224 # If restoring from checkpoint or fast forwarding, the code that does this for 225 # FutureCPUClass is in the Simulation module. If the check passes then the 226 # elastic trace probe is attached to the switch CPUs. 227 if options.elastic_trace_en and options.checkpoint_restore == None and \ 228 not options.fast_forward: 229 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 230 231 CacheConfig.config_cache(options, test_sys) 232 233 MemConfig.config_mem(options, test_sys) 234 235 return test_sys 236 237def build_drive_system(np): 238 # driver system CPU is always simple, so is the memory 239 # Note this is an assignment of a class, not an instance. 240 DriveCPUClass = AtomicSimpleCPU 241 drive_mem_mode = 'atomic' 242 DriveMemClass = SimpleMemory 243 244 cmdline = cmd_line_template() 245 if buildEnv['TARGET_ISA'] == 'alpha': 246 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 247 elif buildEnv['TARGET_ISA'] == 'mips': 248 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 249 elif buildEnv['TARGET_ISA'] == 'sparc': 250 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 251 elif buildEnv['TARGET_ISA'] == 'x86': 252 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 253 cmdline=cmdline) 254 elif buildEnv['TARGET_ISA'] == 'arm': 255 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 256 bm[1], options.dtb_filename, cmdline=cmdline, 257 ignore_dtb=options.generate_dtb) 258 259 # Create a top-level voltage domain 260 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 261 262 # Create a source clock for the system and set the clock period 263 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 264 voltage_domain = drive_sys.voltage_domain) 265 266 # Create a CPU voltage domain 267 drive_sys.cpu_voltage_domain = VoltageDomain() 268 269 # Create a source clock for the CPUs and set the clock period 270 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 271 voltage_domain = 272 drive_sys.cpu_voltage_domain) 273 274 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 275 cpu_id=0) 276 drive_sys.cpu.createThreads() 277 drive_sys.cpu.createInterruptController() 278 drive_sys.cpu.connectAllPorts(drive_sys.membus) 279 if options.fastmem: 280 drive_sys.cpu.fastmem = True 281 if options.kernel is not None: 282 drive_sys.kernel = binary(options.kernel) 283 284 if is_kvm_cpu(DriveCPUClass): 285 drive_sys.kvm_vm = KvmVM() 286 287 drive_sys.iobridge = Bridge(delay='50ns', 288 ranges = drive_sys.mem_ranges) 289 drive_sys.iobridge.slave = drive_sys.iobus.master 290 drive_sys.iobridge.master = drive_sys.membus.slave 291 292 # Create the appropriate memory controllers and connect them to the 293 # memory bus 294 drive_sys.mem_ctrls = [DriveMemClass(range = r) 295 for r in drive_sys.mem_ranges] 296 for i in xrange(len(drive_sys.mem_ctrls)): 297 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 298 299 drive_sys.init_param = options.init_param 300 301 return drive_sys 302 303# Add options 304parser = optparse.OptionParser() 305Options.addCommonOptions(parser) 306Options.addFSOptions(parser) 307 308# Add the ruby specific and protocol specific options 309if '--ruby' in sys.argv: 310 Ruby.define_options(parser) 311 312(options, args) = parser.parse_args() 313 314if args: 315 print("Error: script doesn't take any positional arguments") 316 sys.exit(1) 317 318# system under test can be any CPU 319(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 320 321# Match the memories with the CPUs, based on the options for the test system 322TestMemClass = Simulation.setMemClass(options) 323 324if options.benchmark: 325 try: 326 bm = Benchmarks[options.benchmark] 327 except KeyError: 328 print("Error benchmark %s has not been defined." % options.benchmark) 329 print("Valid benchmarks are: %s" % DefinedBenchmarks) 330 sys.exit(1) 331else: 332 if options.dual: 333 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 334 mem=options.mem_size, os_type=options.os_type), 335 SysConfig(disk=options.disk_image, rootdev=options.root_device, 336 mem=options.mem_size, os_type=options.os_type)] 337 else: 338 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 339 mem=options.mem_size, os_type=options.os_type)] 340 341np = options.num_cpus 342 343test_sys = build_test_system(np) 344if len(bm) == 2: 345 drive_sys = build_drive_system(np) 346 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 347elif len(bm) == 1 and options.dist: 348 # This system is part of a dist-gem5 simulation 349 root = makeDistRoot(test_sys, 350 options.dist_rank, 351 options.dist_size, 352 options.dist_server_name, 353 options.dist_server_port, 354 options.dist_sync_repeat, 355 options.dist_sync_start, 356 options.ethernet_linkspeed, 357 options.ethernet_linkdelay, 358 options.etherdump); 359elif len(bm) == 1: 360 root = Root(full_system=True, system=test_sys) 361else: 362 print("Error I don't know how to create more than 2 systems.") 363 sys.exit(1) 364 365if options.timesync: 366 root.time_sync_enable = True 367 368if options.frame_capture: 369 VncServer.frame_capture = True 370 371if buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb: 372 # Sanity checks 373 if options.dtb_filename: 374 fatal("--generate-dtb and --dtb-filename cannot be specified at the"\ 375 "same time.") 376 377 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]: 378 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \ 379 "platforms, unless custom hardware models have been equipped "\ 380 "with generation functionality.") 381 382 # Generate a Device Tree 383 def create_dtb_for_system(system, filename): 384 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1) 385 rootNode = system.generateDeviceTree(state) 386 387 fdt = Fdt() 388 fdt.add_rootnode(rootNode) 389 dtb_filename = os.path.join(m5.options.outdir, filename) 390 return fdt.writeDtbFile(dtb_filename) 391 392 for sysname in ('system', 'testsys', 'drivesys'): 393 if hasattr(root, sysname): 394 sys = getattr(root, sysname) 395 sys.dtb_filename = create_dtb_for_system(sys, '%s.dtb' % sysname) 396 397Simulation.setWorkCountOptions(test_sys, options) 398Simulation.run(options, root, test_sys, FutureClass) 399