fs.py revision 12475
1# Copyright (c) 2010-2013, 2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 15# Copyright (c) 2006-2007 The Regents of The University of Michigan 16# All rights reserved. 17# 18# Redistribution and use in source and binary forms, with or without 19# modification, are permitted provided that the following conditions are 20# met: redistributions of source code must retain the above copyright 21# notice, this list of conditions and the following disclaimer; 22# redistributions in binary form must reproduce the above copyright 23# notice, this list of conditions and the following disclaimer in the 24# documentation and/or other materials provided with the distribution; 25# neither the name of the copyright holders nor the names of its 26# contributors may be used to endorse or promote products derived from 27# this software without specific prior written permission. 28# 29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40# 41# Authors: Ali Saidi 42# Brad Beckmann 43 44import optparse 45import sys 46 47import m5 48from m5.defines import buildEnv 49from m5.objects import * 50from m5.util import addToPath, fatal, warn 51from m5.util.fdthelper import * 52 53addToPath('../') 54 55from ruby import Ruby 56 57from common.FSConfig import * 58from common.SysPaths import * 59from common.Benchmarks import * 60from common import Simulation 61from common import CacheConfig 62from common import MemConfig 63from common import CpuConfig 64from common.Caches import * 65from common import Options 66 67 68# Check if KVM support has been enabled, we might need to do VM 69# configuration if that's the case. 70have_kvm_support = 'BaseKvmCPU' in globals() 71def is_kvm_cpu(cpu_class): 72 return have_kvm_support and cpu_class != None and \ 73 issubclass(cpu_class, BaseKvmCPU) 74 75def cmd_line_template(): 76 if options.command_line and options.command_line_file: 77 print "Error: --command-line and --command-line-file are " \ 78 "mutually exclusive" 79 sys.exit(1) 80 if options.command_line: 81 return options.command_line 82 if options.command_line_file: 83 return open(options.command_line_file).read().strip() 84 return None 85 86def build_test_system(np): 87 cmdline = cmd_line_template() 88 if buildEnv['TARGET_ISA'] == "alpha": 89 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 90 cmdline=cmdline) 91 elif buildEnv['TARGET_ISA'] == "mips": 92 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 93 elif buildEnv['TARGET_ISA'] == "sparc": 94 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 95 elif buildEnv['TARGET_ISA'] == "x86": 96 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 97 options.ruby, cmdline=cmdline) 98 elif buildEnv['TARGET_ISA'] == "arm": 99 test_sys = makeArmSystem(test_mem_mode, options.machine_type, 100 options.num_cpus, bm[0], options.dtb_filename, 101 bare_metal=options.bare_metal, 102 cmdline=cmdline, 103 ignore_dtb=options.generate_dtb, 104 external_memory= 105 options.external_memory_system, 106 ruby=options.ruby, 107 security=options.enable_security_extensions) 108 if options.enable_context_switch_stats_dump: 109 test_sys.enable_context_switch_stats_dump = True 110 else: 111 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 112 113 # Set the cache line size for the entire system 114 test_sys.cache_line_size = options.cacheline_size 115 116 # Create a top-level voltage domain 117 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 118 119 # Create a source clock for the system and set the clock period 120 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 121 voltage_domain = test_sys.voltage_domain) 122 123 # Create a CPU voltage domain 124 test_sys.cpu_voltage_domain = VoltageDomain() 125 126 # Create a source clock for the CPUs and set the clock period 127 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 128 voltage_domain = 129 test_sys.cpu_voltage_domain) 130 131 if options.kernel is not None: 132 test_sys.kernel = binary(options.kernel) 133 134 if options.script is not None: 135 test_sys.readfile = options.script 136 137 if options.lpae: 138 test_sys.have_lpae = True 139 140 if options.virtualisation: 141 test_sys.have_virtualization = True 142 143 test_sys.init_param = options.init_param 144 145 # For now, assign all the CPUs to the same clock domain 146 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 147 for i in xrange(np)] 148 149 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 150 test_sys.kvm_vm = KvmVM() 151 152 if options.ruby: 153 Ruby.create_system(options, True, test_sys, test_sys.iobus, 154 test_sys._dma_ports) 155 156 # Create a seperate clock domain for Ruby 157 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 158 voltage_domain = test_sys.voltage_domain) 159 160 # Connect the ruby io port to the PIO bus, 161 # assuming that there is just one such port. 162 test_sys.iobus.master = test_sys.ruby._io_port.slave 163 164 for (i, cpu) in enumerate(test_sys.cpu): 165 # 166 # Tie the cpu ports to the correct ruby system ports 167 # 168 cpu.clk_domain = test_sys.cpu_clk_domain 169 cpu.createThreads() 170 cpu.createInterruptController() 171 172 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 173 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 174 175 if buildEnv['TARGET_ISA'] in ("x86", "arm"): 176 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 177 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 178 179 if buildEnv['TARGET_ISA'] in "x86": 180 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 181 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 182 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 183 184 else: 185 if options.caches or options.l2cache: 186 # By default the IOCache runs at the system clock 187 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 188 test_sys.iocache.cpu_side = test_sys.iobus.master 189 test_sys.iocache.mem_side = test_sys.membus.slave 190 elif not options.external_memory_system: 191 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 192 test_sys.iobridge.slave = test_sys.iobus.master 193 test_sys.iobridge.master = test_sys.membus.slave 194 195 # Sanity check 196 if options.fastmem: 197 if TestCPUClass != AtomicSimpleCPU: 198 fatal("Fastmem can only be used with atomic CPU!") 199 if (options.caches or options.l2cache): 200 fatal("You cannot use fastmem in combination with caches!") 201 202 if options.simpoint_profile: 203 if not options.fastmem: 204 # Atomic CPU checked with fastmem option already 205 fatal("SimPoint generation should be done with atomic cpu and fastmem") 206 if np > 1: 207 fatal("SimPoint generation not supported with more than one CPUs") 208 209 for i in xrange(np): 210 if options.fastmem: 211 test_sys.cpu[i].fastmem = True 212 if options.simpoint_profile: 213 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 214 if options.checker: 215 test_sys.cpu[i].addCheckerCpu() 216 test_sys.cpu[i].createThreads() 217 218 # If elastic tracing is enabled when not restoring from checkpoint and 219 # when not fast forwarding using the atomic cpu, then check that the 220 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 221 # passes then attach the elastic trace probe. 222 # If restoring from checkpoint or fast forwarding, the code that does this for 223 # FutureCPUClass is in the Simulation module. If the check passes then the 224 # elastic trace probe is attached to the switch CPUs. 225 if options.elastic_trace_en and options.checkpoint_restore == None and \ 226 not options.fast_forward: 227 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 228 229 CacheConfig.config_cache(options, test_sys) 230 231 MemConfig.config_mem(options, test_sys) 232 233 return test_sys 234 235def build_drive_system(np): 236 # driver system CPU is always simple, so is the memory 237 # Note this is an assignment of a class, not an instance. 238 DriveCPUClass = AtomicSimpleCPU 239 drive_mem_mode = 'atomic' 240 DriveMemClass = SimpleMemory 241 242 cmdline = cmd_line_template() 243 if buildEnv['TARGET_ISA'] == 'alpha': 244 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 245 elif buildEnv['TARGET_ISA'] == 'mips': 246 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 247 elif buildEnv['TARGET_ISA'] == 'sparc': 248 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 249 elif buildEnv['TARGET_ISA'] == 'x86': 250 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 251 cmdline=cmdline) 252 elif buildEnv['TARGET_ISA'] == 'arm': 253 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 254 bm[1], options.dtb_filename, cmdline=cmdline, 255 ignore_dtb=options.generate_dtb) 256 257 # Create a top-level voltage domain 258 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 259 260 # Create a source clock for the system and set the clock period 261 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 262 voltage_domain = drive_sys.voltage_domain) 263 264 # Create a CPU voltage domain 265 drive_sys.cpu_voltage_domain = VoltageDomain() 266 267 # Create a source clock for the CPUs and set the clock period 268 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 269 voltage_domain = 270 drive_sys.cpu_voltage_domain) 271 272 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 273 cpu_id=0) 274 drive_sys.cpu.createThreads() 275 drive_sys.cpu.createInterruptController() 276 drive_sys.cpu.connectAllPorts(drive_sys.membus) 277 if options.fastmem: 278 drive_sys.cpu.fastmem = True 279 if options.kernel is not None: 280 drive_sys.kernel = binary(options.kernel) 281 282 if is_kvm_cpu(DriveCPUClass): 283 drive_sys.kvm_vm = KvmVM() 284 285 drive_sys.iobridge = Bridge(delay='50ns', 286 ranges = drive_sys.mem_ranges) 287 drive_sys.iobridge.slave = drive_sys.iobus.master 288 drive_sys.iobridge.master = drive_sys.membus.slave 289 290 # Create the appropriate memory controllers and connect them to the 291 # memory bus 292 drive_sys.mem_ctrls = [DriveMemClass(range = r) 293 for r in drive_sys.mem_ranges] 294 for i in xrange(len(drive_sys.mem_ctrls)): 295 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 296 297 drive_sys.init_param = options.init_param 298 299 return drive_sys 300 301# Add options 302parser = optparse.OptionParser() 303Options.addCommonOptions(parser) 304Options.addFSOptions(parser) 305 306# Add the ruby specific and protocol specific options 307if '--ruby' in sys.argv: 308 Ruby.define_options(parser) 309 310(options, args) = parser.parse_args() 311 312if args: 313 print "Error: script doesn't take any positional arguments" 314 sys.exit(1) 315 316# system under test can be any CPU 317(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 318 319# Match the memories with the CPUs, based on the options for the test system 320TestMemClass = Simulation.setMemClass(options) 321 322if options.benchmark: 323 try: 324 bm = Benchmarks[options.benchmark] 325 except KeyError: 326 print "Error benchmark %s has not been defined." % options.benchmark 327 print "Valid benchmarks are: %s" % DefinedBenchmarks 328 sys.exit(1) 329else: 330 if options.dual: 331 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 332 mem=options.mem_size, os_type=options.os_type), 333 SysConfig(disk=options.disk_image, rootdev=options.root_device, 334 mem=options.mem_size, os_type=options.os_type)] 335 else: 336 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 337 mem=options.mem_size, os_type=options.os_type)] 338 339np = options.num_cpus 340 341test_sys = build_test_system(np) 342if len(bm) == 2: 343 drive_sys = build_drive_system(np) 344 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 345elif len(bm) == 1 and options.dist: 346 # This system is part of a dist-gem5 simulation 347 root = makeDistRoot(test_sys, 348 options.dist_rank, 349 options.dist_size, 350 options.dist_server_name, 351 options.dist_server_port, 352 options.dist_sync_repeat, 353 options.dist_sync_start, 354 options.ethernet_linkspeed, 355 options.ethernet_linkdelay, 356 options.etherdump); 357elif len(bm) == 1: 358 root = Root(full_system=True, system=test_sys) 359else: 360 print "Error I don't know how to create more than 2 systems." 361 sys.exit(1) 362 363if options.timesync: 364 root.time_sync_enable = True 365 366if options.frame_capture: 367 VncServer.frame_capture = True 368 369if buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb: 370 # Sanity checks 371 if options.dtb_filename: 372 fatal("--generate-dtb and --dtb-filename cannot be specified at the"\ 373 "same time.") 374 375 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]: 376 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \ 377 "platforms, unless custom hardware models have been equipped "\ 378 "with generation functionality.") 379 380 # Generate a Device Tree 381 def create_dtb_for_system(system, filename): 382 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1) 383 rootNode = system.generateDeviceTree(state) 384 385 fdt = Fdt() 386 fdt.add_rootnode(rootNode) 387 dtb_filename = os.path.join(m5.options.outdir, filename) 388 return fdt.writeDtbFile(dtb_filename) 389 390 for sysname in ('system', 'testsys', 'drivesys'): 391 if hasattr(root, sysname): 392 sys = getattr(root, sysname) 393 sys.dtb_filename = create_dtb_for_system(sys, '%s.dtb' % sysname) 394 395elif buildEnv['TARGET_ISA'] != "arm" and options.generate_dtb: 396 fatal("Can only generate dtb files for ARM systems.") 397 398Simulation.setWorkCountOptions(test_sys, options) 399Simulation.run(options, root, test_sys, FutureClass) 400