fs.py revision 12395:322bb93e5f06
17584SAli.Saidi@arm.com# Copyright (c) 2010-2013, 2016 ARM Limited 27584SAli.Saidi@arm.com# All rights reserved. 37584SAli.Saidi@arm.com# 47584SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57584SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67584SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77584SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87584SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97584SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107584SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117584SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127584SAli.Saidi@arm.com# 137584SAli.Saidi@arm.com# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 147584SAli.Saidi@arm.com# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 157584SAli.Saidi@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 167584SAli.Saidi@arm.com# All rights reserved. 177584SAli.Saidi@arm.com# 187584SAli.Saidi@arm.com# Redistribution and use in source and binary forms, with or without 197584SAli.Saidi@arm.com# modification, are permitted provided that the following conditions are 207584SAli.Saidi@arm.com# met: redistributions of source code must retain the above copyright 217584SAli.Saidi@arm.com# notice, this list of conditions and the following disclaimer; 227584SAli.Saidi@arm.com# redistributions in binary form must reproduce the above copyright 237584SAli.Saidi@arm.com# notice, this list of conditions and the following disclaimer in the 247584SAli.Saidi@arm.com# documentation and/or other materials provided with the distribution; 257584SAli.Saidi@arm.com# neither the name of the copyright holders nor the names of its 267584SAli.Saidi@arm.com# contributors may be used to endorse or promote products derived from 277584SAli.Saidi@arm.com# this software without specific prior written permission. 287584SAli.Saidi@arm.com# 297584SAli.Saidi@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307584SAli.Saidi@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317584SAli.Saidi@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327584SAli.Saidi@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337584SAli.Saidi@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347584SAli.Saidi@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357584SAli.Saidi@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367584SAli.Saidi@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377584SAli.Saidi@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387584SAli.Saidi@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397584SAli.Saidi@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407584SAli.Saidi@arm.com# 417584SAli.Saidi@arm.com# Authors: Ali Saidi 427584SAli.Saidi@arm.com# Brad Beckmann 437584SAli.Saidi@arm.com 447584SAli.Saidi@arm.comimport optparse 457584SAli.Saidi@arm.comimport sys 467584SAli.Saidi@arm.com 477584SAli.Saidi@arm.comimport m5 487584SAli.Saidi@arm.comfrom m5.defines import buildEnv 497584SAli.Saidi@arm.comfrom m5.objects import * 507584SAli.Saidi@arm.comfrom m5.util import addToPath, fatal, warn 517584SAli.Saidi@arm.com 527584SAli.Saidi@arm.comaddToPath('../') 537584SAli.Saidi@arm.com 547584SAli.Saidi@arm.comfrom ruby import Ruby 557584SAli.Saidi@arm.com 567584SAli.Saidi@arm.comfrom common.FSConfig import * 577584SAli.Saidi@arm.comfrom common.SysPaths import * 587584SAli.Saidi@arm.comfrom common.Benchmarks import * 597584SAli.Saidi@arm.comfrom common import Simulation 607584SAli.Saidi@arm.comfrom common import CacheConfig 617587SAli.Saidi@arm.comfrom common import MemConfig 627584SAli.Saidi@arm.comfrom common import CpuConfig 637584SAli.Saidi@arm.comfrom common.Caches import * 647584SAli.Saidi@arm.comfrom common import Options 657584SAli.Saidi@arm.com 667584SAli.Saidi@arm.com 677584SAli.Saidi@arm.com# Check if KVM support has been enabled, we might need to do VM 687584SAli.Saidi@arm.com# configuration if that's the case. 697584SAli.Saidi@arm.comhave_kvm_support = 'BaseKvmCPU' in globals() 707584SAli.Saidi@arm.comdef is_kvm_cpu(cpu_class): 717584SAli.Saidi@arm.com return have_kvm_support and cpu_class != None and \ 727584SAli.Saidi@arm.com issubclass(cpu_class, BaseKvmCPU) 737584SAli.Saidi@arm.com 747584SAli.Saidi@arm.comdef cmd_line_template(): 757584SAli.Saidi@arm.com if options.command_line and options.command_line_file: 767584SAli.Saidi@arm.com print "Error: --command-line and --command-line-file are " \ 777584SAli.Saidi@arm.com "mutually exclusive" 787584SAli.Saidi@arm.com sys.exit(1) 797584SAli.Saidi@arm.com if options.command_line: 807584SAli.Saidi@arm.com return options.command_line 817584SAli.Saidi@arm.com if options.command_line_file: 827584SAli.Saidi@arm.com return open(options.command_line_file).read().strip() 837584SAli.Saidi@arm.com return None 847584SAli.Saidi@arm.com 857584SAli.Saidi@arm.comdef build_test_system(np): 867584SAli.Saidi@arm.com cmdline = cmd_line_template() 877584SAli.Saidi@arm.com if buildEnv['TARGET_ISA'] == "alpha": 887584SAli.Saidi@arm.com test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 897584SAli.Saidi@arm.com cmdline=cmdline) 907584SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == "mips": 917584SAli.Saidi@arm.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 927584SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == "sparc": 937584SAli.Saidi@arm.com test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 947584SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == "x86": 957584SAli.Saidi@arm.com test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 967584SAli.Saidi@arm.com options.ruby, cmdline=cmdline) 977584SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == "arm": 987584SAli.Saidi@arm.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, 997584SAli.Saidi@arm.com options.num_cpus, bm[0], options.dtb_filename, 1007584SAli.Saidi@arm.com bare_metal=options.bare_metal, 1017584SAli.Saidi@arm.com cmdline=cmdline, 1027584SAli.Saidi@arm.com external_memory=options.external_memory_system, 1037584SAli.Saidi@arm.com ruby=options.ruby, 1047584SAli.Saidi@arm.com security=options.enable_security_extensions) 1057584SAli.Saidi@arm.com if options.enable_context_switch_stats_dump: 1067584SAli.Saidi@arm.com test_sys.enable_context_switch_stats_dump = True 1077584SAli.Saidi@arm.com else: 1087584SAli.Saidi@arm.com fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1097584SAli.Saidi@arm.com 1107584SAli.Saidi@arm.com # Set the cache line size for the entire system 1117584SAli.Saidi@arm.com test_sys.cache_line_size = options.cacheline_size 1127584SAli.Saidi@arm.com 1137584SAli.Saidi@arm.com # Create a top-level voltage domain 1147584SAli.Saidi@arm.com test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1157584SAli.Saidi@arm.com 1167584SAli.Saidi@arm.com # Create a source clock for the system and set the clock period 1177584SAli.Saidi@arm.com test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1187584SAli.Saidi@arm.com voltage_domain = test_sys.voltage_domain) 1197584SAli.Saidi@arm.com 1207584SAli.Saidi@arm.com # Create a CPU voltage domain 1217584SAli.Saidi@arm.com test_sys.cpu_voltage_domain = VoltageDomain() 1227584SAli.Saidi@arm.com 1237584SAli.Saidi@arm.com # Create a source clock for the CPUs and set the clock period 1247584SAli.Saidi@arm.com test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1257584SAli.Saidi@arm.com voltage_domain = 1267584SAli.Saidi@arm.com test_sys.cpu_voltage_domain) 1277584SAli.Saidi@arm.com 1287584SAli.Saidi@arm.com if options.kernel is not None: 1297584SAli.Saidi@arm.com test_sys.kernel = binary(options.kernel) 1307584SAli.Saidi@arm.com 1317584SAli.Saidi@arm.com if options.script is not None: 1327584SAli.Saidi@arm.com test_sys.readfile = options.script 1337584SAli.Saidi@arm.com 1347584SAli.Saidi@arm.com if options.lpae: 1357584SAli.Saidi@arm.com test_sys.have_lpae = True 1367584SAli.Saidi@arm.com 1377584SAli.Saidi@arm.com if options.virtualisation: 1387584SAli.Saidi@arm.com test_sys.have_virtualization = True 1397584SAli.Saidi@arm.com 1407584SAli.Saidi@arm.com test_sys.init_param = options.init_param 1417584SAli.Saidi@arm.com 1427584SAli.Saidi@arm.com # For now, assign all the CPUs to the same clock domain 1437584SAli.Saidi@arm.com test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1447584SAli.Saidi@arm.com for i in xrange(np)] 1457584SAli.Saidi@arm.com 1467584SAli.Saidi@arm.com if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1477584SAli.Saidi@arm.com test_sys.kvm_vm = KvmVM() 1487584SAli.Saidi@arm.com 1497584SAli.Saidi@arm.com if options.ruby: 1507584SAli.Saidi@arm.com Ruby.create_system(options, True, test_sys, test_sys.iobus, 1517584SAli.Saidi@arm.com test_sys._dma_ports) 1527584SAli.Saidi@arm.com 1537584SAli.Saidi@arm.com # Create a seperate clock domain for Ruby 1547584SAli.Saidi@arm.com test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1557584SAli.Saidi@arm.com voltage_domain = test_sys.voltage_domain) 1567584SAli.Saidi@arm.com 1577584SAli.Saidi@arm.com # Connect the ruby io port to the PIO bus, 1587584SAli.Saidi@arm.com # assuming that there is just one such port. 1597584SAli.Saidi@arm.com test_sys.iobus.master = test_sys.ruby._io_port.slave 1607584SAli.Saidi@arm.com 1617584SAli.Saidi@arm.com for (i, cpu) in enumerate(test_sys.cpu): 1627584SAli.Saidi@arm.com # 1637584SAli.Saidi@arm.com # Tie the cpu ports to the correct ruby system ports 1647584SAli.Saidi@arm.com # 1657584SAli.Saidi@arm.com cpu.clk_domain = test_sys.cpu_clk_domain 1667584SAli.Saidi@arm.com cpu.createThreads() 1677584SAli.Saidi@arm.com cpu.createInterruptController() 168 169 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 170 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 171 172 if buildEnv['TARGET_ISA'] in ("x86", "arm"): 173 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 174 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 175 176 if buildEnv['TARGET_ISA'] in "x86": 177 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 178 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 179 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 180 181 else: 182 if options.caches or options.l2cache: 183 # By default the IOCache runs at the system clock 184 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 185 test_sys.iocache.cpu_side = test_sys.iobus.master 186 test_sys.iocache.mem_side = test_sys.membus.slave 187 elif not options.external_memory_system: 188 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 189 test_sys.iobridge.slave = test_sys.iobus.master 190 test_sys.iobridge.master = test_sys.membus.slave 191 192 # Sanity check 193 if options.fastmem: 194 if TestCPUClass != AtomicSimpleCPU: 195 fatal("Fastmem can only be used with atomic CPU!") 196 if (options.caches or options.l2cache): 197 fatal("You cannot use fastmem in combination with caches!") 198 199 if options.simpoint_profile: 200 if not options.fastmem: 201 # Atomic CPU checked with fastmem option already 202 fatal("SimPoint generation should be done with atomic cpu and fastmem") 203 if np > 1: 204 fatal("SimPoint generation not supported with more than one CPUs") 205 206 for i in xrange(np): 207 if options.fastmem: 208 test_sys.cpu[i].fastmem = True 209 if options.simpoint_profile: 210 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 211 if options.checker: 212 test_sys.cpu[i].addCheckerCpu() 213 test_sys.cpu[i].createThreads() 214 215 # If elastic tracing is enabled when not restoring from checkpoint and 216 # when not fast forwarding using the atomic cpu, then check that the 217 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 218 # passes then attach the elastic trace probe. 219 # If restoring from checkpoint or fast forwarding, the code that does this for 220 # FutureCPUClass is in the Simulation module. If the check passes then the 221 # elastic trace probe is attached to the switch CPUs. 222 if options.elastic_trace_en and options.checkpoint_restore == None and \ 223 not options.fast_forward: 224 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 225 226 CacheConfig.config_cache(options, test_sys) 227 228 MemConfig.config_mem(options, test_sys) 229 230 return test_sys 231 232def build_drive_system(np): 233 # driver system CPU is always simple, so is the memory 234 # Note this is an assignment of a class, not an instance. 235 DriveCPUClass = AtomicSimpleCPU 236 drive_mem_mode = 'atomic' 237 DriveMemClass = SimpleMemory 238 239 cmdline = cmd_line_template() 240 if buildEnv['TARGET_ISA'] == 'alpha': 241 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 242 elif buildEnv['TARGET_ISA'] == 'mips': 243 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 244 elif buildEnv['TARGET_ISA'] == 'sparc': 245 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 246 elif buildEnv['TARGET_ISA'] == 'x86': 247 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 248 cmdline=cmdline) 249 elif buildEnv['TARGET_ISA'] == 'arm': 250 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 251 bm[1], options.dtb_filename, cmdline=cmdline) 252 253 # Create a top-level voltage domain 254 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 255 256 # Create a source clock for the system and set the clock period 257 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 258 voltage_domain = drive_sys.voltage_domain) 259 260 # Create a CPU voltage domain 261 drive_sys.cpu_voltage_domain = VoltageDomain() 262 263 # Create a source clock for the CPUs and set the clock period 264 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 265 voltage_domain = 266 drive_sys.cpu_voltage_domain) 267 268 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 269 cpu_id=0) 270 drive_sys.cpu.createThreads() 271 drive_sys.cpu.createInterruptController() 272 drive_sys.cpu.connectAllPorts(drive_sys.membus) 273 if options.fastmem: 274 drive_sys.cpu.fastmem = True 275 if options.kernel is not None: 276 drive_sys.kernel = binary(options.kernel) 277 278 if is_kvm_cpu(DriveCPUClass): 279 drive_sys.kvm_vm = KvmVM() 280 281 drive_sys.iobridge = Bridge(delay='50ns', 282 ranges = drive_sys.mem_ranges) 283 drive_sys.iobridge.slave = drive_sys.iobus.master 284 drive_sys.iobridge.master = drive_sys.membus.slave 285 286 # Create the appropriate memory controllers and connect them to the 287 # memory bus 288 drive_sys.mem_ctrls = [DriveMemClass(range = r) 289 for r in drive_sys.mem_ranges] 290 for i in xrange(len(drive_sys.mem_ctrls)): 291 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 292 293 drive_sys.init_param = options.init_param 294 295 return drive_sys 296 297# Add options 298parser = optparse.OptionParser() 299Options.addCommonOptions(parser) 300Options.addFSOptions(parser) 301 302# Add the ruby specific and protocol specific options 303if '--ruby' in sys.argv: 304 Ruby.define_options(parser) 305 306(options, args) = parser.parse_args() 307 308if args: 309 print "Error: script doesn't take any positional arguments" 310 sys.exit(1) 311 312# system under test can be any CPU 313(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 314 315# Match the memories with the CPUs, based on the options for the test system 316TestMemClass = Simulation.setMemClass(options) 317 318if options.benchmark: 319 try: 320 bm = Benchmarks[options.benchmark] 321 except KeyError: 322 print "Error benchmark %s has not been defined." % options.benchmark 323 print "Valid benchmarks are: %s" % DefinedBenchmarks 324 sys.exit(1) 325else: 326 if options.dual: 327 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 328 mem=options.mem_size, os_type=options.os_type), 329 SysConfig(disk=options.disk_image, rootdev=options.root_device, 330 mem=options.mem_size, os_type=options.os_type)] 331 else: 332 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 333 mem=options.mem_size, os_type=options.os_type)] 334 335np = options.num_cpus 336 337test_sys = build_test_system(np) 338if len(bm) == 2: 339 drive_sys = build_drive_system(np) 340 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 341elif len(bm) == 1 and options.dist: 342 # This system is part of a dist-gem5 simulation 343 root = makeDistRoot(test_sys, 344 options.dist_rank, 345 options.dist_size, 346 options.dist_server_name, 347 options.dist_server_port, 348 options.dist_sync_repeat, 349 options.dist_sync_start, 350 options.ethernet_linkspeed, 351 options.ethernet_linkdelay, 352 options.etherdump); 353elif len(bm) == 1: 354 root = Root(full_system=True, system=test_sys) 355else: 356 print "Error I don't know how to create more than 2 systems." 357 sys.exit(1) 358 359if options.timesync: 360 root.time_sync_enable = True 361 362if options.frame_capture: 363 VncServer.frame_capture = True 364 365Simulation.setWorkCountOptions(test_sys, options) 366Simulation.run(options, root, test_sys, FutureClass) 367