fs.py revision 11662:004d34b65092 
1# Copyright (c) 2010-2013, 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42#          Brad Beckmann
43
44import optparse
45import sys
46
47import m5
48from m5.defines import buildEnv
49from m5.objects import *
50from m5.util import addToPath, fatal
51
52addToPath('../common')
53addToPath('../ruby')
54addToPath('../network')
55
56import Ruby
57import Network
58
59from FSConfig import *
60from SysPaths import *
61from Benchmarks import *
62import Simulation
63import CacheConfig
64import MemConfig
65from Caches import *
66import Options
67
68
69# Check if KVM support has been enabled, we might need to do VM
70# configuration if that's the case.
71have_kvm_support = 'BaseKvmCPU' in globals()
72def is_kvm_cpu(cpu_class):
73    return have_kvm_support and cpu_class != None and \
74        issubclass(cpu_class, BaseKvmCPU)
75
76def cmd_line_template():
77    if options.command_line and options.command_line_file:
78        print "Error: --command-line and --command-line-file are " \
79              "mutually exclusive"
80        sys.exit(1)
81    if options.command_line:
82        return options.command_line
83    if options.command_line_file:
84        return open(options.command_line_file).read().strip()
85    return None
86
87def build_test_system(np):
88    cmdline = cmd_line_template()
89    if buildEnv['TARGET_ISA'] == "alpha":
90        test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
91                                        cmdline=cmdline)
92    elif buildEnv['TARGET_ISA'] == "mips":
93        test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
94    elif buildEnv['TARGET_ISA'] == "sparc":
95        test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
96    elif buildEnv['TARGET_ISA'] == "x86":
97        test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
98                options.ruby, cmdline=cmdline)
99    elif buildEnv['TARGET_ISA'] == "arm":
100        test_sys = makeArmSystem(test_mem_mode, options.machine_type,
101                                 options.num_cpus, bm[0], options.dtb_filename,
102                                 bare_metal=options.bare_metal,
103                                 cmdline=cmdline,
104                                 external_memory=options.external_memory_system,
105                                 ruby=options.ruby)
106        if options.enable_context_switch_stats_dump:
107            test_sys.enable_context_switch_stats_dump = True
108    else:
109        fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
110
111    # Set the cache line size for the entire system
112    test_sys.cache_line_size = options.cacheline_size
113
114    # Create a top-level voltage domain
115    test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
116
117    # Create a source clock for the system and set the clock period
118    test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
119            voltage_domain = test_sys.voltage_domain)
120
121    # Create a CPU voltage domain
122    test_sys.cpu_voltage_domain = VoltageDomain()
123
124    # Create a source clock for the CPUs and set the clock period
125    test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
126                                             voltage_domain =
127                                             test_sys.cpu_voltage_domain)
128
129    if options.kernel is not None:
130        test_sys.kernel = binary(options.kernel)
131
132    if options.script is not None:
133        test_sys.readfile = options.script
134
135    if options.lpae:
136        test_sys.have_lpae = True
137
138    if options.virtualisation:
139        test_sys.have_virtualization = True
140
141    test_sys.init_param = options.init_param
142
143    # For now, assign all the CPUs to the same clock domain
144    test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
145                    for i in xrange(np)]
146
147    if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
148        test_sys.vm = KvmVM()
149
150    if options.ruby:
151        # Check for timing mode because ruby does not support atomic accesses
152        if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
153            print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
154            sys.exit(1)
155
156        Ruby.create_system(options, True, test_sys, test_sys.iobus,
157                           test_sys._dma_ports)
158
159        # Create a seperate clock domain for Ruby
160        test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
161                                        voltage_domain = test_sys.voltage_domain)
162
163        # Connect the ruby io port to the PIO bus,
164        # assuming that there is just one such port.
165        test_sys.iobus.master = test_sys.ruby._io_port.slave
166
167        for (i, cpu) in enumerate(test_sys.cpu):
168            #
169            # Tie the cpu ports to the correct ruby system ports
170            #
171            cpu.clk_domain = test_sys.cpu_clk_domain
172            cpu.createThreads()
173            cpu.createInterruptController()
174
175            cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
176            cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
177
178            if buildEnv['TARGET_ISA'] in ("x86", "arm"):
179                cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
180                cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
181
182            if buildEnv['TARGET_ISA'] in "x86":
183                cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
184                cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
185                cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
186
187    else:
188        if options.caches or options.l2cache:
189            # By default the IOCache runs at the system clock
190            test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
191            test_sys.iocache.cpu_side = test_sys.iobus.master
192            test_sys.iocache.mem_side = test_sys.membus.slave
193        elif not options.external_memory_system:
194            test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
195            test_sys.iobridge.slave = test_sys.iobus.master
196            test_sys.iobridge.master = test_sys.membus.slave
197
198        # Sanity check
199        if options.fastmem:
200            if TestCPUClass != AtomicSimpleCPU:
201                fatal("Fastmem can only be used with atomic CPU!")
202            if (options.caches or options.l2cache):
203                fatal("You cannot use fastmem in combination with caches!")
204
205        if options.simpoint_profile:
206            if not options.fastmem:
207                # Atomic CPU checked with fastmem option already
208                fatal("SimPoint generation should be done with atomic cpu and fastmem")
209            if np > 1:
210                fatal("SimPoint generation not supported with more than one CPUs")
211
212        for i in xrange(np):
213            if options.fastmem:
214                test_sys.cpu[i].fastmem = True
215            if options.simpoint_profile:
216                test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
217            if options.checker:
218                test_sys.cpu[i].addCheckerCpu()
219            test_sys.cpu[i].createThreads()
220
221        # If elastic tracing is enabled when not restoring from checkpoint and
222        # when not fast forwarding using the atomic cpu, then check that the
223        # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
224        # passes then attach the elastic trace probe.
225        # If restoring from checkpoint or fast forwarding, the code that does this for
226        # FutureCPUClass is in the Simulation module. If the check passes then the
227        # elastic trace probe is attached to the switch CPUs.
228        if options.elastic_trace_en and options.checkpoint_restore == None and \
229            not options.fast_forward:
230            CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
231
232        CacheConfig.config_cache(options, test_sys)
233
234        MemConfig.config_mem(options, test_sys)
235
236    return test_sys
237
238def build_drive_system(np):
239    # driver system CPU is always simple, so is the memory
240    # Note this is an assignment of a class, not an instance.
241    DriveCPUClass = AtomicSimpleCPU
242    drive_mem_mode = 'atomic'
243    DriveMemClass = SimpleMemory
244
245    cmdline = cmd_line_template()
246    if buildEnv['TARGET_ISA'] == 'alpha':
247        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline)
248    elif buildEnv['TARGET_ISA'] == 'mips':
249        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
250    elif buildEnv['TARGET_ISA'] == 'sparc':
251        drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
252    elif buildEnv['TARGET_ISA'] == 'x86':
253        drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
254                                       cmdline=cmdline)
255    elif buildEnv['TARGET_ISA'] == 'arm':
256        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
257                                  bm[1], options.dtb_filename, cmdline=cmdline)
258
259    # Create a top-level voltage domain
260    drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
261
262    # Create a source clock for the system and set the clock period
263    drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
264            voltage_domain = drive_sys.voltage_domain)
265
266    # Create a CPU voltage domain
267    drive_sys.cpu_voltage_domain = VoltageDomain()
268
269    # Create a source clock for the CPUs and set the clock period
270    drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
271                                              voltage_domain =
272                                              drive_sys.cpu_voltage_domain)
273
274    drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
275                                  cpu_id=0)
276    drive_sys.cpu.createThreads()
277    drive_sys.cpu.createInterruptController()
278    drive_sys.cpu.connectAllPorts(drive_sys.membus)
279    if options.fastmem:
280        drive_sys.cpu.fastmem = True
281    if options.kernel is not None:
282        drive_sys.kernel = binary(options.kernel)
283
284    if is_kvm_cpu(DriveCPUClass):
285        drive_sys.vm = KvmVM()
286
287    drive_sys.iobridge = Bridge(delay='50ns',
288                                ranges = drive_sys.mem_ranges)
289    drive_sys.iobridge.slave = drive_sys.iobus.master
290    drive_sys.iobridge.master = drive_sys.membus.slave
291
292    # Create the appropriate memory controllers and connect them to the
293    # memory bus
294    drive_sys.mem_ctrls = [DriveMemClass(range = r)
295                           for r in drive_sys.mem_ranges]
296    for i in xrange(len(drive_sys.mem_ctrls)):
297        drive_sys.mem_ctrls[i].port = drive_sys.membus.master
298
299    drive_sys.init_param = options.init_param
300
301    return drive_sys
302
303# Add options
304parser = optparse.OptionParser()
305Options.addCommonOptions(parser)
306Options.addFSOptions(parser)
307
308# Add the ruby specific and protocol specific options
309if '--ruby' in sys.argv:
310    Ruby.define_options(parser)
311    Network.define_options(parser)
312
313(options, args) = parser.parse_args()
314
315if args:
316    print "Error: script doesn't take any positional arguments"
317    sys.exit(1)
318
319# system under test can be any CPU
320(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
321
322# Match the memories with the CPUs, based on the options for the test system
323TestMemClass = Simulation.setMemClass(options)
324
325if options.benchmark:
326    try:
327        bm = Benchmarks[options.benchmark]
328    except KeyError:
329        print "Error benchmark %s has not been defined." % options.benchmark
330        print "Valid benchmarks are: %s" % DefinedBenchmarks
331        sys.exit(1)
332else:
333    if options.dual:
334        bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
335                        mem=options.mem_size, os_type=options.os_type),
336              SysConfig(disk=options.disk_image, rootdev=options.root_device,
337                        mem=options.mem_size, os_type=options.os_type)]
338    else:
339        bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
340                        mem=options.mem_size, os_type=options.os_type)]
341
342np = options.num_cpus
343
344test_sys = build_test_system(np)
345if len(bm) == 2:
346    drive_sys = build_drive_system(np)
347    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
348elif len(bm) == 1 and options.dist:
349    # This system is part of a dist-gem5 simulation
350    root = makeDistRoot(test_sys,
351                        options.dist_rank,
352                        options.dist_size,
353                        options.dist_server_name,
354                        options.dist_server_port,
355                        options.dist_sync_repeat,
356                        options.dist_sync_start,
357                        options.ethernet_linkspeed,
358                        options.ethernet_linkdelay,
359                        options.etherdump);
360elif len(bm) == 1:
361    root = Root(full_system=True, system=test_sys)
362else:
363    print "Error I don't know how to create more than 2 systems."
364    sys.exit(1)
365
366if options.timesync:
367    root.time_sync_enable = True
368
369if options.frame_capture:
370    VncServer.frame_capture = True
371
372Simulation.setWorkCountOptions(test_sys, options)
373Simulation.run(options, root, test_sys, FutureClass)
374