fs.py revision 10524:fff17530cef6
111308Santhony.gutierrez@amd.com# Copyright (c) 2010-2013 ARM Limited 211308Santhony.gutierrez@amd.com# All rights reserved. 311308Santhony.gutierrez@amd.com# 411308Santhony.gutierrez@amd.com# The license below extends only to copyright in the software and shall 511308Santhony.gutierrez@amd.com# not be construed as granting a license to any other intellectual 611308Santhony.gutierrez@amd.com# property including but not limited to intellectual property relating 711308Santhony.gutierrez@amd.com# to a hardware implementation of the functionality of the software 811308Santhony.gutierrez@amd.com# licensed hereunder. You may use the software subject to the license 911308Santhony.gutierrez@amd.com# terms below provided that you ensure that this notice is replicated 1011308Santhony.gutierrez@amd.com# unmodified and in its entirety in all distributions of the software, 1111308Santhony.gutierrez@amd.com# modified or unmodified, in source code or in binary form. 1211308Santhony.gutierrez@amd.com# 1311308Santhony.gutierrez@amd.com# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 1411308Santhony.gutierrez@amd.com# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 1511308Santhony.gutierrez@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 1611308Santhony.gutierrez@amd.com# All rights reserved. 1711308Santhony.gutierrez@amd.com# 1811308Santhony.gutierrez@amd.com# Redistribution and use in source and binary forms, with or without 1911308Santhony.gutierrez@amd.com# modification, are permitted provided that the following conditions are 2011308Santhony.gutierrez@amd.com# met: redistributions of source code must retain the above copyright 2111308Santhony.gutierrez@amd.com# notice, this list of conditions and the following disclaimer; 2211308Santhony.gutierrez@amd.com# redistributions in binary form must reproduce the above copyright 2311308Santhony.gutierrez@amd.com# notice, this list of conditions and the following disclaimer in the 2411308Santhony.gutierrez@amd.com# documentation and/or other materials provided with the distribution; 2511308Santhony.gutierrez@amd.com# neither the name of the copyright holders nor the names of its 2611308Santhony.gutierrez@amd.com# contributors may be used to endorse or promote products derived from 2711308Santhony.gutierrez@amd.com# this software without specific prior written permission. 2811308Santhony.gutierrez@amd.com# 2911308Santhony.gutierrez@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011308Santhony.gutierrez@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111308Santhony.gutierrez@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211308Santhony.gutierrez@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311308Santhony.gutierrez@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411308Santhony.gutierrez@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511308Santhony.gutierrez@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611308Santhony.gutierrez@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711308Santhony.gutierrez@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811308Santhony.gutierrez@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911308Santhony.gutierrez@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011308Santhony.gutierrez@amd.com# 4111308Santhony.gutierrez@amd.com# Authors: Ali Saidi 4211308Santhony.gutierrez@amd.com# Brad Beckmann 4311308Santhony.gutierrez@amd.com 4411308Santhony.gutierrez@amd.comimport optparse 4511308Santhony.gutierrez@amd.comimport sys 4611308Santhony.gutierrez@amd.com 4711308Santhony.gutierrez@amd.comimport m5 4811308Santhony.gutierrez@amd.comfrom m5.defines import buildEnv 4911308Santhony.gutierrez@amd.comfrom m5.objects import * 5011308Santhony.gutierrez@amd.comfrom m5.util import addToPath, fatal 5111308Santhony.gutierrez@amd.com 5211308Santhony.gutierrez@amd.comaddToPath('../common') 5311308Santhony.gutierrez@amd.comaddToPath('../ruby') 5411308Santhony.gutierrez@amd.com 5511308Santhony.gutierrez@amd.comimport Ruby 5611308Santhony.gutierrez@amd.com 5711308Santhony.gutierrez@amd.comfrom FSConfig import * 5811308Santhony.gutierrez@amd.comfrom SysPaths import * 5911308Santhony.gutierrez@amd.comfrom Benchmarks import * 6011308Santhony.gutierrez@amd.comimport Simulation 6111308Santhony.gutierrez@amd.comimport CacheConfig 6211308Santhony.gutierrez@amd.comimport MemConfig 6311308Santhony.gutierrez@amd.comfrom Caches import * 6411308Santhony.gutierrez@amd.comimport Options 6511308Santhony.gutierrez@amd.com 6611308Santhony.gutierrez@amd.com 6711308Santhony.gutierrez@amd.com# Check if KVM support has been enabled, we might need to do VM 6811308Santhony.gutierrez@amd.com# configuration if that's the case. 6911308Santhony.gutierrez@amd.comhave_kvm_support = 'BaseKvmCPU' in globals() 7011308Santhony.gutierrez@amd.comdef is_kvm_cpu(cpu_class): 7111308Santhony.gutierrez@amd.com return have_kvm_support and cpu_class != None and \ 7211308Santhony.gutierrez@amd.com issubclass(cpu_class, BaseKvmCPU) 7311308Santhony.gutierrez@amd.com 7411308Santhony.gutierrez@amd.comdef build_test_system(np): 7511308Santhony.gutierrez@amd.com if buildEnv['TARGET_ISA'] == "alpha": 7611308Santhony.gutierrez@amd.com test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby) 7711308Santhony.gutierrez@amd.com elif buildEnv['TARGET_ISA'] == "mips": 7811308Santhony.gutierrez@amd.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 7911308Santhony.gutierrez@amd.com elif buildEnv['TARGET_ISA'] == "sparc": 8011308Santhony.gutierrez@amd.com test_sys = makeSparcSystem(test_mem_mode, bm[0]) 8111308Santhony.gutierrez@amd.com elif buildEnv['TARGET_ISA'] == "x86": 8211308Santhony.gutierrez@amd.com test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 8311308Santhony.gutierrez@amd.com options.ruby) 8411308Santhony.gutierrez@amd.com elif buildEnv['TARGET_ISA'] == "arm": 8511308Santhony.gutierrez@amd.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, 8611308Santhony.gutierrez@amd.com options.num_cpus, bm[0], options.dtb_filename, 8711308Santhony.gutierrez@amd.com bare_metal=options.bare_metal) 8811308Santhony.gutierrez@amd.com if options.enable_context_switch_stats_dump: 8911308Santhony.gutierrez@amd.com test_sys.enable_context_switch_stats_dump = True 9011308Santhony.gutierrez@amd.com else: 9111308Santhony.gutierrez@amd.com fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 9211308Santhony.gutierrez@amd.com 9311308Santhony.gutierrez@amd.com # Set the cache line size for the entire system 9411308Santhony.gutierrez@amd.com test_sys.cache_line_size = options.cacheline_size 9511308Santhony.gutierrez@amd.com 9611308Santhony.gutierrez@amd.com # Create a top-level voltage domain 9711308Santhony.gutierrez@amd.com test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 9811308Santhony.gutierrez@amd.com 9911308Santhony.gutierrez@amd.com # Create a source clock for the system and set the clock period 10011308Santhony.gutierrez@amd.com test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 10111308Santhony.gutierrez@amd.com voltage_domain = test_sys.voltage_domain) 10211308Santhony.gutierrez@amd.com 10311308Santhony.gutierrez@amd.com # Create a CPU voltage domain 10411308Santhony.gutierrez@amd.com test_sys.cpu_voltage_domain = VoltageDomain() 10511308Santhony.gutierrez@amd.com 10611308Santhony.gutierrez@amd.com # Create a source clock for the CPUs and set the clock period 10711308Santhony.gutierrez@amd.com test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 10811308Santhony.gutierrez@amd.com voltage_domain = 10911308Santhony.gutierrez@amd.com test_sys.cpu_voltage_domain) 11011308Santhony.gutierrez@amd.com 11111308Santhony.gutierrez@amd.com if options.kernel is not None: 11211308Santhony.gutierrez@amd.com test_sys.kernel = binary(options.kernel) 11311308Santhony.gutierrez@amd.com 11411308Santhony.gutierrez@amd.com if options.script is not None: 11511308Santhony.gutierrez@amd.com test_sys.readfile = options.script 11611308Santhony.gutierrez@amd.com 11711308Santhony.gutierrez@amd.com if options.lpae: 11811308Santhony.gutierrez@amd.com test_sys.have_lpae = True 11911308Santhony.gutierrez@amd.com 12011308Santhony.gutierrez@amd.com if options.virtualisation: 12111308Santhony.gutierrez@amd.com test_sys.have_virtualization = True 12211308Santhony.gutierrez@amd.com 12311308Santhony.gutierrez@amd.com test_sys.init_param = options.init_param 12411308Santhony.gutierrez@amd.com 12511308Santhony.gutierrez@amd.com # For now, assign all the CPUs to the same clock domain 12611308Santhony.gutierrez@amd.com test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 12711308Santhony.gutierrez@amd.com for i in xrange(np)] 12811308Santhony.gutierrez@amd.com 12911308Santhony.gutierrez@amd.com if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 13011308Santhony.gutierrez@amd.com test_sys.vm = KvmVM() 13111308Santhony.gutierrez@amd.com 13211308Santhony.gutierrez@amd.com if options.ruby: 13311308Santhony.gutierrez@amd.com # Check for timing mode because ruby does not support atomic accesses 13411308Santhony.gutierrez@amd.com if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 13511308Santhony.gutierrez@amd.com print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 13611308Santhony.gutierrez@amd.com sys.exit(1) 13711308Santhony.gutierrez@amd.com 13811308Santhony.gutierrez@amd.com Ruby.create_system(options, True, test_sys, test_sys.iobus, 13911308Santhony.gutierrez@amd.com test_sys._dma_ports) 14011308Santhony.gutierrez@amd.com 14111308Santhony.gutierrez@amd.com # Create a seperate clock domain for Ruby 14211308Santhony.gutierrez@amd.com test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 14311308Santhony.gutierrez@amd.com voltage_domain = test_sys.voltage_domain) 14411308Santhony.gutierrez@amd.com 14511308Santhony.gutierrez@amd.com for (i, cpu) in enumerate(test_sys.cpu): 14611308Santhony.gutierrez@amd.com # 14711308Santhony.gutierrez@amd.com # Tie the cpu ports to the correct ruby system ports 14811308Santhony.gutierrez@amd.com # 14911308Santhony.gutierrez@amd.com cpu.clk_domain = test_sys.cpu_clk_domain 15011308Santhony.gutierrez@amd.com cpu.createThreads() 15111308Santhony.gutierrez@amd.com cpu.createInterruptController() 15211308Santhony.gutierrez@amd.com 15311308Santhony.gutierrez@amd.com cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 15411308Santhony.gutierrez@amd.com cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 15511308Santhony.gutierrez@amd.com 15611308Santhony.gutierrez@amd.com if buildEnv['TARGET_ISA'] == "x86": 15711308Santhony.gutierrez@amd.com cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 15811308Santhony.gutierrez@amd.com cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 15911308Santhony.gutierrez@amd.com 16011308Santhony.gutierrez@amd.com cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master 16111308Santhony.gutierrez@amd.com cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave 16211308Santhony.gutierrez@amd.com cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master 16311308Santhony.gutierrez@amd.com 16411534Sjohn.kalamatianos@amd.com # Connect the ruby io port to the PIO bus, 16511534Sjohn.kalamatianos@amd.com # assuming that there is just one such port. 16611308Santhony.gutierrez@amd.com test_sys.iobus.master = test_sys.ruby._io_port.slave 16711308Santhony.gutierrez@amd.com 16811308Santhony.gutierrez@amd.com else: 16911308Santhony.gutierrez@amd.com if options.caches or options.l2cache: 17011308Santhony.gutierrez@amd.com # By default the IOCache runs at the system clock 17111308Santhony.gutierrez@amd.com test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 17211308Santhony.gutierrez@amd.com test_sys.iocache.cpu_side = test_sys.iobus.master 17311308Santhony.gutierrez@amd.com test_sys.iocache.mem_side = test_sys.membus.slave 17411308Santhony.gutierrez@amd.com else: 17511308Santhony.gutierrez@amd.com test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 17611308Santhony.gutierrez@amd.com test_sys.iobridge.slave = test_sys.iobus.master 17711308Santhony.gutierrez@amd.com test_sys.iobridge.master = test_sys.membus.slave 17811308Santhony.gutierrez@amd.com 17911308Santhony.gutierrez@amd.com # Sanity check 18011308Santhony.gutierrez@amd.com if options.fastmem: 18111308Santhony.gutierrez@amd.com if TestCPUClass != AtomicSimpleCPU: 18211308Santhony.gutierrez@amd.com fatal("Fastmem can only be used with atomic CPU!") 18311308Santhony.gutierrez@amd.com if (options.caches or options.l2cache): 18411308Santhony.gutierrez@amd.com fatal("You cannot use fastmem in combination with caches!") 18511308Santhony.gutierrez@amd.com 18611308Santhony.gutierrez@amd.com for i in xrange(np): 18711308Santhony.gutierrez@amd.com if options.fastmem: 18811308Santhony.gutierrez@amd.com test_sys.cpu[i].fastmem = True 18911308Santhony.gutierrez@amd.com if options.checker: 19011308Santhony.gutierrez@amd.com test_sys.cpu[i].addCheckerCpu() 19111308Santhony.gutierrez@amd.com test_sys.cpu[i].createThreads() 19211308Santhony.gutierrez@amd.com 19311308Santhony.gutierrez@amd.com CacheConfig.config_cache(options, test_sys) 19411308Santhony.gutierrez@amd.com MemConfig.config_mem(options, test_sys) 19511308Santhony.gutierrez@amd.com 19611308Santhony.gutierrez@amd.com return test_sys 19711308Santhony.gutierrez@amd.com 19811308Santhony.gutierrez@amd.comdef build_drive_system(np): 19911308Santhony.gutierrez@amd.com # driver system CPU is always simple, so is the memory 20011308Santhony.gutierrez@amd.com # Note this is an assignment of a class, not an instance. 20111308Santhony.gutierrez@amd.com DriveCPUClass = AtomicSimpleCPU 20211308Santhony.gutierrez@amd.com drive_mem_mode = 'atomic' 20311308Santhony.gutierrez@amd.com DriveMemClass = SimpleMemory 20411308Santhony.gutierrez@amd.com 20511308Santhony.gutierrez@amd.com if buildEnv['TARGET_ISA'] == 'alpha': 20611308Santhony.gutierrez@amd.com drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 20711308Santhony.gutierrez@amd.com elif buildEnv['TARGET_ISA'] == 'mips': 20811308Santhony.gutierrez@amd.com drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 20911308Santhony.gutierrez@amd.com elif buildEnv['TARGET_ISA'] == 'sparc': 21011308Santhony.gutierrez@amd.com drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 21111308Santhony.gutierrez@amd.com elif buildEnv['TARGET_ISA'] == 'x86': 21211308Santhony.gutierrez@amd.com drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1]) 21311308Santhony.gutierrez@amd.com elif buildEnv['TARGET_ISA'] == 'arm': 21411308Santhony.gutierrez@amd.com drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 21511308Santhony.gutierrez@amd.com 21611308Santhony.gutierrez@amd.com # Create a top-level voltage domain 21711308Santhony.gutierrez@amd.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 21811308Santhony.gutierrez@amd.com 21911308Santhony.gutierrez@amd.com # Create a source clock for the system and set the clock period 22011308Santhony.gutierrez@amd.com drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 22111308Santhony.gutierrez@amd.com voltage_domain = drive_sys.voltage_domain) 22211308Santhony.gutierrez@amd.com 22311308Santhony.gutierrez@amd.com # Create a CPU voltage domain 22411308Santhony.gutierrez@amd.com drive_sys.cpu_voltage_domain = VoltageDomain() 22511308Santhony.gutierrez@amd.com 22611308Santhony.gutierrez@amd.com # Create a source clock for the CPUs and set the clock period 22711308Santhony.gutierrez@amd.com drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 22811308Santhony.gutierrez@amd.com voltage_domain = 22911308Santhony.gutierrez@amd.com drive_sys.cpu_voltage_domain) 23011308Santhony.gutierrez@amd.com 23111308Santhony.gutierrez@amd.com drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 23211308Santhony.gutierrez@amd.com cpu_id=0) 23311308Santhony.gutierrez@amd.com drive_sys.cpu.createThreads() 23411308Santhony.gutierrez@amd.com drive_sys.cpu.createInterruptController() 23511308Santhony.gutierrez@amd.com drive_sys.cpu.connectAllPorts(drive_sys.membus) 23611308Santhony.gutierrez@amd.com if options.fastmem: 23711308Santhony.gutierrez@amd.com drive_sys.cpu.fastmem = True 23811308Santhony.gutierrez@amd.com if options.kernel is not None: 23911308Santhony.gutierrez@amd.com drive_sys.kernel = binary(options.kernel) 24011308Santhony.gutierrez@amd.com 24111308Santhony.gutierrez@amd.com if is_kvm_cpu(DriveCPUClass): 24211308Santhony.gutierrez@amd.com drive_sys.vm = KvmVM() 24311308Santhony.gutierrez@amd.com 24411308Santhony.gutierrez@amd.com drive_sys.iobridge = Bridge(delay='50ns', 24511308Santhony.gutierrez@amd.com ranges = drive_sys.mem_ranges) 24611308Santhony.gutierrez@amd.com drive_sys.iobridge.slave = drive_sys.iobus.master 24711308Santhony.gutierrez@amd.com drive_sys.iobridge.master = drive_sys.membus.slave 24811308Santhony.gutierrez@amd.com 24911308Santhony.gutierrez@amd.com # Create the appropriate memory controllers and connect them to the 25011308Santhony.gutierrez@amd.com # memory bus 25111308Santhony.gutierrez@amd.com drive_sys.mem_ctrls = [DriveMemClass(range = r) 25211308Santhony.gutierrez@amd.com for r in drive_sys.mem_ranges] 25311308Santhony.gutierrez@amd.com for i in xrange(len(drive_sys.mem_ctrls)): 25411308Santhony.gutierrez@amd.com drive_sys.mem_ctrls[i].port = drive_sys.membus.master 25511308Santhony.gutierrez@amd.com 25611308Santhony.gutierrez@amd.com drive_sys.init_param = options.init_param 25711657Salexandru.dutu@amd.com 25811308Santhony.gutierrez@amd.com return drive_sys 25911657Salexandru.dutu@amd.com 26011657Salexandru.dutu@amd.com# Add options 26111308Santhony.gutierrez@amd.comparser = optparse.OptionParser() 26211308Santhony.gutierrez@amd.comOptions.addCommonOptions(parser) 26311308Santhony.gutierrez@amd.comOptions.addFSOptions(parser) 26411308Santhony.gutierrez@amd.com 26511308Santhony.gutierrez@amd.com# Add the ruby specific and protocol specific options 26611308Santhony.gutierrez@amd.comif '--ruby' in sys.argv: 26711308Santhony.gutierrez@amd.com Ruby.define_options(parser) 26811308Santhony.gutierrez@amd.com 26911308Santhony.gutierrez@amd.com(options, args) = parser.parse_args() 27011308Santhony.gutierrez@amd.com 27111308Santhony.gutierrez@amd.comif args: 27211308Santhony.gutierrez@amd.com print "Error: script doesn't take any positional arguments" 27311308Santhony.gutierrez@amd.com sys.exit(1) 27411308Santhony.gutierrez@amd.com 27511308Santhony.gutierrez@amd.com# system under test can be any CPU 27611308Santhony.gutierrez@amd.com(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 27711308Santhony.gutierrez@amd.com 27811308Santhony.gutierrez@amd.com# Match the memories with the CPUs, based on the options for the test system 27911308Santhony.gutierrez@amd.comTestMemClass = Simulation.setMemClass(options) 28011308Santhony.gutierrez@amd.com 28111308Santhony.gutierrez@amd.comif options.benchmark: 28211308Santhony.gutierrez@amd.com try: 28311308Santhony.gutierrez@amd.com bm = Benchmarks[options.benchmark] 28411308Santhony.gutierrez@amd.com except KeyError: 28511308Santhony.gutierrez@amd.com print "Error benchmark %s has not been defined." % options.benchmark 28611308Santhony.gutierrez@amd.com print "Valid benchmarks are: %s" % DefinedBenchmarks 28711308Santhony.gutierrez@amd.com sys.exit(1) 28811308Santhony.gutierrez@amd.comelse: 28911308Santhony.gutierrez@amd.com if options.dual: 29011308Santhony.gutierrez@amd.com bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), 29111308Santhony.gutierrez@amd.com SysConfig(disk=options.disk_image, mem=options.mem_size)] 29211308Santhony.gutierrez@amd.com else: 29311308Santhony.gutierrez@amd.com bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 29411308Santhony.gutierrez@amd.com 29511308Santhony.gutierrez@amd.comnp = options.num_cpus 29611308Santhony.gutierrez@amd.com 29711308Santhony.gutierrez@amd.comtest_sys = build_test_system(np) 29811308Santhony.gutierrez@amd.comif len(bm) == 2: 29911308Santhony.gutierrez@amd.com drive_sys = build_drive_system(np) 30011308Santhony.gutierrez@amd.com root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 30111308Santhony.gutierrez@amd.comelif len(bm) == 1: 30211308Santhony.gutierrez@amd.com root = Root(full_system=True, system=test_sys) 30311308Santhony.gutierrez@amd.comelse: 30411695Santhony.gutierrez@amd.com print "Error I don't know how to create more than 2 systems." 30511695Santhony.gutierrez@amd.com sys.exit(1) 30611695Santhony.gutierrez@amd.com 30711695Santhony.gutierrez@amd.comif options.timesync: 30811695Santhony.gutierrez@amd.com root.time_sync_enable = True 30911695Santhony.gutierrez@amd.com 31011695Santhony.gutierrez@amd.comif options.frame_capture: 31111695Santhony.gutierrez@amd.com VncServer.frame_capture = True 31211695Santhony.gutierrez@amd.com 31311695Santhony.gutierrez@amd.comSimulation.setWorkCountOptions(test_sys, options) 31411695Santhony.gutierrez@amd.comSimulation.run(options, root, test_sys, FutureClass) 31511695Santhony.gutierrez@amd.com