fs.py revision 10056:33db5d81c2cb
110431SOmar.Naji@arm.com# Copyright (c) 2010-2013 ARM Limited 211229Sandreas.hansson@arm.com# All rights reserved. 310431SOmar.Naji@arm.com# 410431SOmar.Naji@arm.com# The license below extends only to copyright in the software and shall 510431SOmar.Naji@arm.com# not be construed as granting a license to any other intellectual 611229Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 710431SOmar.Naji@arm.com# to a hardware implementation of the functionality of the software 810431SOmar.Naji@arm.com# licensed hereunder. You may use the software subject to the license 910431SOmar.Naji@arm.com# terms below provided that you ensure that this notice is replicated 1010431SOmar.Naji@arm.com# unmodified and in its entirety in all distributions of the software, 1110431SOmar.Naji@arm.com# modified or unmodified, in source code or in binary form. 1210431SOmar.Naji@arm.com# 1311229Sandreas.hansson@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 1410431SOmar.Naji@arm.com# All rights reserved. 1510431SOmar.Naji@arm.com# 1610431SOmar.Naji@arm.com# Redistribution and use in source and binary forms, with or without 1710431SOmar.Naji@arm.com# modification, are permitted provided that the following conditions are 1810431SOmar.Naji@arm.com# met: redistributions of source code must retain the above copyright 1910431SOmar.Naji@arm.com# notice, this list of conditions and the following disclaimer; 2010431SOmar.Naji@arm.com# redistributions in binary form must reproduce the above copyright 2110431SOmar.Naji@arm.com# notice, this list of conditions and the following disclaimer in the 2210431SOmar.Naji@arm.com# documentation and/or other materials provided with the distribution; 2310431SOmar.Naji@arm.com# neither the name of the copyright holders nor the names of its 2410431SOmar.Naji@arm.com# contributors may be used to endorse or promote products derived from 2510431SOmar.Naji@arm.com# this software without specific prior written permission. 2610431SOmar.Naji@arm.com# 2710431SOmar.Naji@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2810431SOmar.Naji@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2910431SOmar.Naji@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3011229Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3110431SOmar.Naji@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3210431SOmar.Naji@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3310431SOmar.Naji@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3411229Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3510431SOmar.Naji@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3610431SOmar.Naji@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3710431SOmar.Naji@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3810431SOmar.Naji@arm.com# 3910431SOmar.Naji@arm.com# Authors: Ali Saidi 4010431SOmar.Naji@arm.com 4110431SOmar.Naji@arm.comimport optparse 4210431SOmar.Naji@arm.comimport sys 4310431SOmar.Naji@arm.com 4410431SOmar.Naji@arm.comimport m5 4510431SOmar.Naji@arm.comfrom m5.defines import buildEnv 4610431SOmar.Naji@arm.comfrom m5.objects import * 4710431SOmar.Naji@arm.comfrom m5.util import addToPath, fatal 4810431SOmar.Naji@arm.com 4910431SOmar.Naji@arm.comaddToPath('../common') 5010431SOmar.Naji@arm.com 5110431SOmar.Naji@arm.comfrom FSConfig import * 5210431SOmar.Naji@arm.comfrom SysPaths import * 5310431SOmar.Naji@arm.comfrom Benchmarks import * 5410431SOmar.Naji@arm.comimport Simulation 5510431SOmar.Naji@arm.comimport CacheConfig 5610431SOmar.Naji@arm.comimport MemConfig 5710431SOmar.Naji@arm.comfrom Caches import * 5810431SOmar.Naji@arm.comimport Options 5910431SOmar.Naji@arm.com 6010431SOmar.Naji@arm.comparser = optparse.OptionParser() 6110431SOmar.Naji@arm.comOptions.addCommonOptions(parser) 6210431SOmar.Naji@arm.comOptions.addFSOptions(parser) 6310431SOmar.Naji@arm.com 6410431SOmar.Naji@arm.com(options, args) = parser.parse_args() 6510431SOmar.Naji@arm.com 6610431SOmar.Naji@arm.comif args: 6710431SOmar.Naji@arm.com print "Error: script doesn't take any positional arguments" 6810431SOmar.Naji@arm.com sys.exit(1) 6910431SOmar.Naji@arm.com 7010431SOmar.Naji@arm.com# driver system CPU is always simple... note this is an assignment of 7110431SOmar.Naji@arm.com# a class, not an instance. 7210431SOmar.Naji@arm.comDriveCPUClass = AtomicSimpleCPU 7310431SOmar.Naji@arm.comdrive_mem_mode = 'atomic' 7410431SOmar.Naji@arm.com 7510431SOmar.Naji@arm.com# Check if KVM support has been enabled, we might need to do VM 7610431SOmar.Naji@arm.com# configuration if that's the case. 7710431SOmar.Naji@arm.comhave_kvm_support = 'BaseKvmCPU' in globals() 7810431SOmar.Naji@arm.comdef is_kvm_cpu(cpu_class): 7910431SOmar.Naji@arm.com return have_kvm_support and cpu_class != None and \ 8010431SOmar.Naji@arm.com issubclass(cpu_class, BaseKvmCPU) 8110431SOmar.Naji@arm.com 8210431SOmar.Naji@arm.com# system under test can be any CPU 8310431SOmar.Naji@arm.com(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 8410431SOmar.Naji@arm.com 8510431SOmar.Naji@arm.com# Match the memories with the CPUs, the driver system always simple, 8610431SOmar.Naji@arm.com# and based on the options for the test system 8710431SOmar.Naji@arm.comDriveMemClass = SimpleMemory 8810431SOmar.Naji@arm.comTestMemClass = Simulation.setMemClass(options) 8910431SOmar.Naji@arm.com 9010431SOmar.Naji@arm.comif options.benchmark: 9110431SOmar.Naji@arm.com try: 9210431SOmar.Naji@arm.com bm = Benchmarks[options.benchmark] 9310431SOmar.Naji@arm.com except KeyError: 9410431SOmar.Naji@arm.com print "Error benchmark %s has not been defined." % options.benchmark 9510431SOmar.Naji@arm.com print "Valid benchmarks are: %s" % DefinedBenchmarks 9610431SOmar.Naji@arm.com sys.exit(1) 9710431SOmar.Naji@arm.comelse: 9810431SOmar.Naji@arm.com if options.dual: 9910431SOmar.Naji@arm.com bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), 10010431SOmar.Naji@arm.com SysConfig(disk=options.disk_image, mem=options.mem_size)] 10110431SOmar.Naji@arm.com else: 10210431SOmar.Naji@arm.com bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 10310431SOmar.Naji@arm.com 104np = options.num_cpus 105 106if buildEnv['TARGET_ISA'] == "alpha": 107 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 108elif buildEnv['TARGET_ISA'] == "mips": 109 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 110elif buildEnv['TARGET_ISA'] == "sparc": 111 test_sys = makeSparcSystem(test_mem_mode, bm[0]) 112elif buildEnv['TARGET_ISA'] == "x86": 113 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 114elif buildEnv['TARGET_ISA'] == "arm": 115 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 116 options.dtb_filename, 117 bare_metal=options.bare_metal) 118 if options.enable_context_switch_stats_dump: 119 test_sys.enable_context_switch_stats_dump = True 120else: 121 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 122 123# Create a top-level voltage domain 124test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 125 126# Create a source clock for the system and set the clock period 127test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 128 voltage_domain = test_sys.voltage_domain) 129 130# Create a CPU voltage domain 131test_sys.cpu_voltage_domain = VoltageDomain() 132 133# Create a source clock for the CPUs and set the clock period 134test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 135 voltage_domain = 136 test_sys.cpu_voltage_domain) 137 138if options.kernel is not None: 139 test_sys.kernel = binary(options.kernel) 140 141if options.script is not None: 142 test_sys.readfile = options.script 143 144if options.lpae: 145 test_sys.have_lpae = True 146 147if options.virtualisation: 148 test_sys.have_virtualization = True 149 150test_sys.init_param = options.init_param 151 152# For now, assign all the CPUs to the same clock domain 153test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 154 for i in xrange(np)] 155 156if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 157 test_sys.vm = KvmVM() 158 159if options.caches or options.l2cache: 160 # By default the IOCache runs at the system clock 161 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 162 test_sys.iocache.cpu_side = test_sys.iobus.master 163 test_sys.iocache.mem_side = test_sys.membus.slave 164else: 165 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 166 test_sys.iobridge.slave = test_sys.iobus.master 167 test_sys.iobridge.master = test_sys.membus.slave 168 169# Sanity check 170if options.fastmem: 171 if TestCPUClass != AtomicSimpleCPU: 172 fatal("Fastmem can only be used with atomic CPU!") 173 if (options.caches or options.l2cache): 174 fatal("You cannot use fastmem in combination with caches!") 175 176for i in xrange(np): 177 if options.fastmem: 178 test_sys.cpu[i].fastmem = True 179 if options.checker: 180 test_sys.cpu[i].addCheckerCpu() 181 test_sys.cpu[i].createThreads() 182 183CacheConfig.config_cache(options, test_sys) 184MemConfig.config_mem(options, test_sys) 185 186if len(bm) == 2: 187 if buildEnv['TARGET_ISA'] == 'alpha': 188 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 189 elif buildEnv['TARGET_ISA'] == 'mips': 190 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 191 elif buildEnv['TARGET_ISA'] == 'sparc': 192 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 193 elif buildEnv['TARGET_ISA'] == 'x86': 194 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1]) 195 elif buildEnv['TARGET_ISA'] == 'arm': 196 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 197 198 # Create a top-level voltage domain 199 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 200 201 # Create a source clock for the system and set the clock period 202 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) 203 204 # Create a CPU voltage domain 205 drive_sys.cpu_voltage_domain = VoltageDomain() 206 207 # Create a source clock for the CPUs and set the clock period 208 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 209 voltage_domain = 210 drive_sys.cpu_voltage_domain) 211 212 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 213 cpu_id=0) 214 drive_sys.cpu.createThreads() 215 drive_sys.cpu.createInterruptController() 216 drive_sys.cpu.connectAllPorts(drive_sys.membus) 217 if options.fastmem: 218 drive_sys.cpu.fastmem = True 219 if options.kernel is not None: 220 drive_sys.kernel = binary(options.kernel) 221 222 if is_kvm_cpu(DriveCPUClass): 223 drive_sys.vm = KvmVM() 224 225 drive_sys.iobridge = Bridge(delay='50ns', 226 ranges = drive_sys.mem_ranges) 227 drive_sys.iobridge.slave = drive_sys.iobus.master 228 drive_sys.iobridge.master = drive_sys.membus.slave 229 230 # Create the appropriate memory controllers and connect them to the 231 # memory bus 232 drive_sys.mem_ctrls = [DriveMemClass(range = r) 233 for r in drive_sys.mem_ranges] 234 for i in xrange(len(drive_sys.mem_ctrls)): 235 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 236 237 drive_sys.init_param = options.init_param 238 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 239elif len(bm) == 1: 240 root = Root(full_system=True, system=test_sys) 241else: 242 print "Error I don't know how to create more than 2 systems." 243 sys.exit(1) 244 245if options.timesync: 246 root.time_sync_enable = True 247 248if options.frame_capture: 249 VncServer.frame_capture = True 250 251Simulation.setWorkCountOptions(test_sys, options) 252Simulation.run(options, root, test_sys, FutureClass) 253