fs.py revision 10056 
1# Copyright (c) 2010-2013 ARM Limited
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan
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38#
39# Authors: Ali Saidi
40
41import optparse
42import sys
43
44import m5
45from m5.defines import buildEnv
46from m5.objects import *
47from m5.util import addToPath, fatal
48
49addToPath('../common')
50
51from FSConfig import *
52from SysPaths import *
53from Benchmarks import *
54import Simulation
55import CacheConfig
56import MemConfig
57from Caches import *
58import Options
59
60parser = optparse.OptionParser()
61Options.addCommonOptions(parser)
62Options.addFSOptions(parser)
63
64(options, args) = parser.parse_args()
65
66if args:
67    print "Error: script doesn't take any positional arguments"
68    sys.exit(1)
69
70# driver system CPU is always simple... note this is an assignment of
71# a class, not an instance.
72DriveCPUClass = AtomicSimpleCPU
73drive_mem_mode = 'atomic'
74
75# Check if KVM support has been enabled, we might need to do VM
76# configuration if that's the case.
77have_kvm_support = 'BaseKvmCPU' in globals()
78def is_kvm_cpu(cpu_class):
79    return have_kvm_support and cpu_class != None and \
80        issubclass(cpu_class, BaseKvmCPU)
81
82# system under test can be any CPU
83(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
84
85# Match the memories with the CPUs, the driver system always simple,
86# and based on the options for the test system
87DriveMemClass = SimpleMemory
88TestMemClass = Simulation.setMemClass(options)
89
90if options.benchmark:
91    try:
92        bm = Benchmarks[options.benchmark]
93    except KeyError:
94        print "Error benchmark %s has not been defined." % options.benchmark
95        print "Valid benchmarks are: %s" % DefinedBenchmarks
96        sys.exit(1)
97else:
98    if options.dual:
99        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
100              SysConfig(disk=options.disk_image, mem=options.mem_size)]
101    else:
102        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
103
104np = options.num_cpus
105
106if buildEnv['TARGET_ISA'] == "alpha":
107    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
108elif buildEnv['TARGET_ISA'] == "mips":
109    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
110elif buildEnv['TARGET_ISA'] == "sparc":
111    test_sys = makeSparcSystem(test_mem_mode, bm[0])
112elif buildEnv['TARGET_ISA'] == "x86":
113    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
114elif buildEnv['TARGET_ISA'] == "arm":
115    test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
116                             options.dtb_filename,
117                             bare_metal=options.bare_metal)
118    if options.enable_context_switch_stats_dump:
119        test_sys.enable_context_switch_stats_dump = True
120else:
121    fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
122
123# Create a top-level voltage domain
124test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
125
126# Create a source clock for the system and set the clock period
127test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
128                                     voltage_domain = test_sys.voltage_domain)
129
130# Create a CPU voltage domain
131test_sys.cpu_voltage_domain = VoltageDomain()
132
133# Create a source clock for the CPUs and set the clock period
134test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
135                                         voltage_domain =
136                                         test_sys.cpu_voltage_domain)
137
138if options.kernel is not None:
139    test_sys.kernel = binary(options.kernel)
140
141if options.script is not None:
142    test_sys.readfile = options.script
143
144if options.lpae:
145    test_sys.have_lpae = True
146
147if options.virtualisation:
148    test_sys.have_virtualization = True
149
150test_sys.init_param = options.init_param
151
152# For now, assign all the CPUs to the same clock domain
153test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
154                for i in xrange(np)]
155
156if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
157    test_sys.vm = KvmVM()
158
159if options.caches or options.l2cache:
160    # By default the IOCache runs at the system clock
161    test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
162    test_sys.iocache.cpu_side = test_sys.iobus.master
163    test_sys.iocache.mem_side = test_sys.membus.slave
164else:
165    test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
166    test_sys.iobridge.slave = test_sys.iobus.master
167    test_sys.iobridge.master = test_sys.membus.slave
168
169# Sanity check
170if options.fastmem:
171    if TestCPUClass != AtomicSimpleCPU:
172        fatal("Fastmem can only be used with atomic CPU!")
173    if (options.caches or options.l2cache):
174        fatal("You cannot use fastmem in combination with caches!")
175
176for i in xrange(np):
177    if options.fastmem:
178        test_sys.cpu[i].fastmem = True
179    if options.checker:
180        test_sys.cpu[i].addCheckerCpu()
181    test_sys.cpu[i].createThreads()
182
183CacheConfig.config_cache(options, test_sys)
184MemConfig.config_mem(options, test_sys)
185
186if len(bm) == 2:
187    if buildEnv['TARGET_ISA'] == 'alpha':
188        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
189    elif buildEnv['TARGET_ISA'] == 'mips':
190        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
191    elif buildEnv['TARGET_ISA'] == 'sparc':
192        drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
193    elif buildEnv['TARGET_ISA'] == 'x86':
194        drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1])
195    elif buildEnv['TARGET_ISA'] == 'arm':
196        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
197
198    # Create a top-level voltage domain
199    drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
200
201    # Create a source clock for the system and set the clock period
202    drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
203
204    # Create a CPU voltage domain
205    drive_sys.cpu_voltage_domain = VoltageDomain()
206
207    # Create a source clock for the CPUs and set the clock period
208    drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
209                                              voltage_domain =
210                                              drive_sys.cpu_voltage_domain)
211
212    drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
213                                  cpu_id=0)
214    drive_sys.cpu.createThreads()
215    drive_sys.cpu.createInterruptController()
216    drive_sys.cpu.connectAllPorts(drive_sys.membus)
217    if options.fastmem:
218        drive_sys.cpu.fastmem = True
219    if options.kernel is not None:
220        drive_sys.kernel = binary(options.kernel)
221
222    if is_kvm_cpu(DriveCPUClass):
223        drive_sys.vm = KvmVM()
224
225    drive_sys.iobridge = Bridge(delay='50ns',
226                                ranges = drive_sys.mem_ranges)
227    drive_sys.iobridge.slave = drive_sys.iobus.master
228    drive_sys.iobridge.master = drive_sys.membus.slave
229
230    # Create the appropriate memory controllers and connect them to the
231    # memory bus
232    drive_sys.mem_ctrls = [DriveMemClass(range = r)
233                           for r in drive_sys.mem_ranges]
234    for i in xrange(len(drive_sys.mem_ctrls)):
235        drive_sys.mem_ctrls[i].port = drive_sys.membus.master
236
237    drive_sys.init_param = options.init_param
238    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
239elif len(bm) == 1:
240    root = Root(full_system=True, system=test_sys)
241else:
242    print "Error I don't know how to create more than 2 systems."
243    sys.exit(1)
244
245if options.timesync:
246    root.time_sync_enable = True
247
248if options.frame_capture:
249    VncServer.frame_capture = True
250
251Simulation.setWorkCountOptions(test_sys, options)
252Simulation.run(options, root, test_sys, FutureClass)
253