fs.py revision 9827
19793Sakash.bagdia@arm.com# Copyright (c) 2010-2013 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 133970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 143005Sstever@eecs.umich.edu# All rights reserved. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253005Sstever@eecs.umich.edu# this software without specific prior written permission. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383005Sstever@eecs.umich.edu# 393005Sstever@eecs.umich.edu# Authors: Ali Saidi 403005Sstever@eecs.umich.edu 416654Snate@binkert.orgimport optparse 426654Snate@binkert.orgimport sys 432889SN/A 442710SN/Aimport m5 456654Snate@binkert.orgfrom m5.defines import buildEnv 466654Snate@binkert.orgfrom m5.objects import * 476654Snate@binkert.orgfrom m5.util import addToPath, fatal 485457Ssaidi@eecs.umich.edu 496654Snate@binkert.orgaddToPath('../common') 506654Snate@binkert.org 512934SN/Afrom FSConfig import * 522549SN/Afrom SysPaths import * 532995SN/Afrom Benchmarks import * 543395Shsul@eecs.umich.eduimport Simulation 556981SLisa.Hsu@amd.comimport CacheConfig 563448Shsul@eecs.umich.edufrom Caches import * 578920Snilay@cs.wisc.eduimport Options 583444Sktlim@umich.edu 592889SN/Aparser = optparse.OptionParser() 608920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 618920Snilay@cs.wisc.eduOptions.addFSOptions(parser) 623322Shsul@eecs.umich.edu 632710SN/A(options, args) = parser.parse_args() 642710SN/A 652710SN/Aif args: 662710SN/A print "Error: script doesn't take any positional arguments" 672710SN/A sys.exit(1) 682710SN/A 693322Shsul@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of 703304Sstever@eecs.umich.edu# a class, not an instance. 713322Shsul@eecs.umich.eduDriveCPUClass = AtomicSimpleCPU 723322Shsul@eecs.umich.edudrive_mem_mode = 'atomic' 733304Sstever@eecs.umich.edu 749653SAndreas.Sandberg@ARM.com# Check if KVM support has been enabled, we might need to do VM 759653SAndreas.Sandberg@ARM.com# configuration if that's the case. 769653SAndreas.Sandberg@ARM.comhave_kvm_support = 'BaseKvmCPU' in globals() 779653SAndreas.Sandberg@ARM.comdef is_kvm_cpu(cpu_class): 789653SAndreas.Sandberg@ARM.com return have_kvm_support and cpu_class != None and \ 799653SAndreas.Sandberg@ARM.com issubclass(cpu_class, BaseKvmCPU) 809653SAndreas.Sandberg@ARM.com 813481Shsul@eecs.umich.edu# system under test can be any CPU 823481Shsul@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 832566SN/A 849665Sandreas.hansson@arm.com# Match the memories with the CPUs, the driver system always simple, 859665Sandreas.hansson@arm.com# and based on the options for the test system 869665Sandreas.hansson@arm.comDriveMemClass = SimpleMemory 879665Sandreas.hansson@arm.comTestMemClass = Simulation.setMemClass(options) 889665Sandreas.hansson@arm.com 892995SN/Aif options.benchmark: 903304Sstever@eecs.umich.edu try: 913304Sstever@eecs.umich.edu bm = Benchmarks[options.benchmark] 923304Sstever@eecs.umich.edu except KeyError: 932995SN/A print "Error benchmark %s has not been defined." % options.benchmark 942995SN/A print "Valid benchmarks are: %s" % DefinedBenchmarks 952995SN/A sys.exit(1) 962917SN/Aelse: 972995SN/A if options.dual: 988956Sjayneel@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 992995SN/A else: 1008956Sjayneel@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 1013304Sstever@eecs.umich.edu 1026135Sgblack@eecs.umich.edunp = options.num_cpus 1036135Sgblack@eecs.umich.edu 1046654Snate@binkert.orgif buildEnv['TARGET_ISA'] == "alpha": 1059826Sandreas.hansson@arm.com test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 1066654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "mips": 1079826Sandreas.hansson@arm.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 1086654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "sparc": 1099826Sandreas.hansson@arm.com test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1106654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "x86": 1119826Sandreas.hansson@arm.com test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 1127586SAli.Saidi@arm.comelif buildEnv['TARGET_ISA'] == "arm": 1139826Sandreas.hansson@arm.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 1149826Sandreas.hansson@arm.com options.dtb_filename, 1159665Sandreas.hansson@arm.com bare_metal=options.bare_metal) 1163819Shsul@eecs.umich.eduelse: 1179059Snilay@cs.wisc.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1183819Shsul@eecs.umich.edu 1199827Sakash.bagdia@arm.com# Create a top-level voltage domain 1209827Sakash.bagdia@arm.comtest_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1219827Sakash.bagdia@arm.com 1229793Sakash.bagdia@arm.com# Create a source clock for the system and set the clock period 1239827Sakash.bagdia@arm.comtest_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1249827Sakash.bagdia@arm.com voltage_domain = test_sys.voltage_domain) 1259827Sakash.bagdia@arm.com 1269827Sakash.bagdia@arm.com# Create a CPU voltage domain 1279827Sakash.bagdia@arm.comtest_sys.cpu_voltage_domain = VoltageDomain() 1289793Sakash.bagdia@arm.com 1299793Sakash.bagdia@arm.com# Create a source clock for the CPUs and set the clock period 1309827Sakash.bagdia@arm.comtest_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1319827Sakash.bagdia@arm.com voltage_domain = 1329827Sakash.bagdia@arm.com test_sys.cpu_voltage_domain) 1339790Sakash.bagdia@arm.com 1343873Sbinkertn@umich.eduif options.kernel is not None: 1353873Sbinkertn@umich.edu test_sys.kernel = binary(options.kernel) 1363873Sbinkertn@umich.edu 1373873Sbinkertn@umich.eduif options.script is not None: 1383873Sbinkertn@umich.edu test_sys.readfile = options.script 1393873Sbinkertn@umich.edu 1408659SAli.Saidi@ARM.comtest_sys.init_param = options.init_param 1418659SAli.Saidi@ARM.com 1429793Sakash.bagdia@arm.com# For now, assign all the CPUs to the same clock domain 1439793Sakash.bagdia@arm.comtest_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1449793Sakash.bagdia@arm.com for i in xrange(np)] 1453668Srdreslin@umich.edu 1469653SAndreas.Sandberg@ARM.comif is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1479653SAndreas.Sandberg@ARM.com test_sys.vm = KvmVM() 1489653SAndreas.Sandberg@ARM.com 1496636Ssteve.reinhardt@amd.comif options.caches or options.l2cache: 1509788Sakash.bagdia@arm.com # By default the IOCache runs at the system clock 1519788Sakash.bagdia@arm.com test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 1528839Sandreas.hansson@arm.com test_sys.iocache.cpu_side = test_sys.iobus.master 1538839Sandreas.hansson@arm.com test_sys.iocache.mem_side = test_sys.membus.slave 1548713Sandreas.hansson@arm.comelse: 1559408Sandreas.hansson@arm.com test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1568839Sandreas.hansson@arm.com test_sys.iobridge.slave = test_sys.iobus.master 1578839Sandreas.hansson@arm.com test_sys.iobridge.master = test_sys.membus.slave 1585142Ssaidi@eecs.umich.edu 1598926Sandreas.hansson@arm.com# Sanity check 1609317Sandreas.hansson@arm.comif options.fastmem: 1619317Sandreas.hansson@arm.com if TestCPUClass != AtomicSimpleCPU: 1629317Sandreas.hansson@arm.com fatal("Fastmem can only be used with atomic CPU!") 1639317Sandreas.hansson@arm.com if (options.caches or options.l2cache): 1649317Sandreas.hansson@arm.com fatal("You cannot use fastmem in combination with caches!") 1658926Sandreas.hansson@arm.com 1663312Sstever@eecs.umich.edufor i in xrange(np): 1674968Sacolyte@umich.edu if options.fastmem: 1688926Sandreas.hansson@arm.com test_sys.cpu[i].fastmem = True 1698887Sgeoffrey.blake@arm.com if options.checker: 1708887Sgeoffrey.blake@arm.com test_sys.cpu[i].addCheckerCpu() 1719384SAndreas.Sandberg@arm.com test_sys.cpu[i].createThreads() 1728887Sgeoffrey.blake@arm.com 1738887Sgeoffrey.blake@arm.comCacheConfig.config_cache(options, test_sys) 1744968Sacolyte@umich.edu 1759826Sandreas.hansson@arm.com# Create the appropriate memory controllers and connect them to the 1769826Sandreas.hansson@arm.com# memory bus 1779826Sandreas.hansson@arm.comtest_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True) 1789826Sandreas.hansson@arm.com for r in test_sys.mem_ranges] 1799826Sandreas.hansson@arm.comfor i in xrange(len(test_sys.mem_ctrls)): 1809826Sandreas.hansson@arm.com test_sys.mem_ctrls[i].port = test_sys.membus.master 1819826Sandreas.hansson@arm.com 1823005Sstever@eecs.umich.eduif len(bm) == 2: 1836654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'alpha': 1849826Sandreas.hansson@arm.com drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 1856654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1869826Sandreas.hansson@arm.com drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 1876654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'sparc': 1889826Sandreas.hansson@arm.com drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 1896654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1909826Sandreas.hansson@arm.com drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 1917586SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 1929826Sandreas.hansson@arm.com drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 1938661SAli.Saidi@ARM.com 1949827Sakash.bagdia@arm.com # Create a top-level voltage domain 1959827Sakash.bagdia@arm.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1969827Sakash.bagdia@arm.com 1979793Sakash.bagdia@arm.com # Create a source clock for the system and set the clock period 1989793Sakash.bagdia@arm.com drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) 1999790Sakash.bagdia@arm.com 2009827Sakash.bagdia@arm.com # Create a CPU voltage domain 2019827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain = VoltageDomain() 2029827Sakash.bagdia@arm.com 2039793Sakash.bagdia@arm.com # Create a source clock for the CPUs and set the clock period 2049827Sakash.bagdia@arm.com drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2059827Sakash.bagdia@arm.com voltage_domain = 2069827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain) 2079793Sakash.bagdia@arm.com 2089793Sakash.bagdia@arm.com drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2099793Sakash.bagdia@arm.com cpu_id=0) 2109384SAndreas.Sandberg@arm.com drive_sys.cpu.createThreads() 2118863Snilay@cs.wisc.edu drive_sys.cpu.createInterruptController() 2127876Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2134968Sacolyte@umich.edu if options.fastmem: 2148926Sandreas.hansson@arm.com drive_sys.cpu.fastmem = True 2154837Ssaidi@eecs.umich.edu if options.kernel is not None: 2164837Ssaidi@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2179408Sandreas.hansson@arm.com 2189653SAndreas.Sandberg@ARM.com if is_kvm_cpu(DriveCPUClass): 2199653SAndreas.Sandberg@ARM.com drive_sys.vm = KvmVM() 2209653SAndreas.Sandberg@ARM.com 2219164Sandreas.hansson@arm.com drive_sys.iobridge = Bridge(delay='50ns', 2229408Sandreas.hansson@arm.com ranges = drive_sys.mem_ranges) 2238845Sandreas.hansson@arm.com drive_sys.iobridge.slave = drive_sys.iobus.master 2248845Sandreas.hansson@arm.com drive_sys.iobridge.master = drive_sys.membus.slave 2254837Ssaidi@eecs.umich.edu 2269826Sandreas.hansson@arm.com # Create the appropriate memory controllers and connect them to the 2279826Sandreas.hansson@arm.com # memory bus 2289826Sandreas.hansson@arm.com drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True) 2299826Sandreas.hansson@arm.com for r in drive_sys.mem_ranges] 2309826Sandreas.hansson@arm.com for i in xrange(len(drive_sys.mem_ctrls)): 2319826Sandreas.hansson@arm.com drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2329826Sandreas.hansson@arm.com 2338659SAli.Saidi@ARM.com drive_sys.init_param = options.init_param 2348801Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 2353005Sstever@eecs.umich.eduelif len(bm) == 1: 2368801Sgblack@eecs.umich.edu root = Root(full_system=True, system=test_sys) 2373005Sstever@eecs.umich.eduelse: 2383005Sstever@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 2393005Sstever@eecs.umich.edu sys.exit(1) 2402566SN/A 2417861Sgblack@eecs.umich.eduif options.timesync: 2427861Sgblack@eecs.umich.edu root.time_sync_enable = True 2437861Sgblack@eecs.umich.edu 2448635Schris.emmons@arm.comif options.frame_capture: 2458635Schris.emmons@arm.com VncServer.frame_capture = True 2468635Schris.emmons@arm.com 2479061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options) 2483481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 249