fs.py revision 9790
18926Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited
27586SAli.Saidi@arm.com# All rights reserved.
37586SAli.Saidi@arm.com#
47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall
57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual
67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating
77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software
87586SAli.Saidi@arm.com# licensed hereunder.  You may use the software subject to the license
97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated
107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software,
117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form.
127586SAli.Saidi@arm.com#
133970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
143005Sstever@eecs.umich.edu# All rights reserved.
153005Sstever@eecs.umich.edu#
163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution;
233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its
243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
253005Sstever@eecs.umich.edu# this software without specific prior written permission.
263005Sstever@eecs.umich.edu#
273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
383005Sstever@eecs.umich.edu#
393005Sstever@eecs.umich.edu# Authors: Ali Saidi
403005Sstever@eecs.umich.edu
416654Snate@binkert.orgimport optparse
426654Snate@binkert.orgimport sys
432889SN/A
442710SN/Aimport m5
456654Snate@binkert.orgfrom m5.defines import buildEnv
466654Snate@binkert.orgfrom m5.objects import *
476654Snate@binkert.orgfrom m5.util import addToPath, fatal
485457Ssaidi@eecs.umich.edu
496654Snate@binkert.orgaddToPath('../common')
506654Snate@binkert.org
512934SN/Afrom FSConfig import *
522549SN/Afrom SysPaths import *
532995SN/Afrom Benchmarks import *
543395Shsul@eecs.umich.eduimport Simulation
556981SLisa.Hsu@amd.comimport CacheConfig
563448Shsul@eecs.umich.edufrom Caches import *
578920Snilay@cs.wisc.eduimport Options
583444Sktlim@umich.edu
592889SN/Aparser = optparse.OptionParser()
608920Snilay@cs.wisc.eduOptions.addCommonOptions(parser)
618920Snilay@cs.wisc.eduOptions.addFSOptions(parser)
623322Shsul@eecs.umich.edu
632710SN/A(options, args) = parser.parse_args()
642710SN/A
652710SN/Aif args:
662710SN/A    print "Error: script doesn't take any positional arguments"
672710SN/A    sys.exit(1)
682710SN/A
693322Shsul@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of
703304Sstever@eecs.umich.edu# a class, not an instance.
713322Shsul@eecs.umich.eduDriveCPUClass = AtomicSimpleCPU
723322Shsul@eecs.umich.edudrive_mem_mode = 'atomic'
733304Sstever@eecs.umich.edu
749653SAndreas.Sandberg@ARM.com# Check if KVM support has been enabled, we might need to do VM
759653SAndreas.Sandberg@ARM.com# configuration if that's the case.
769653SAndreas.Sandberg@ARM.comhave_kvm_support = 'BaseKvmCPU' in globals()
779653SAndreas.Sandberg@ARM.comdef is_kvm_cpu(cpu_class):
789653SAndreas.Sandberg@ARM.com    return have_kvm_support and cpu_class != None and \
799653SAndreas.Sandberg@ARM.com        issubclass(cpu_class, BaseKvmCPU)
809653SAndreas.Sandberg@ARM.com
813481Shsul@eecs.umich.edu# system under test can be any CPU
823481Shsul@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
832566SN/A
849789Sakash.bagdia@arm.comTestCPUClass.clock = options.cpu_clock
859789Sakash.bagdia@arm.comDriveCPUClass.clock = options.cpu_clock
862995SN/A
879665Sandreas.hansson@arm.com# Match the memories with the CPUs, the driver system always simple,
889665Sandreas.hansson@arm.com# and based on the options for the test system
899665Sandreas.hansson@arm.comDriveMemClass = SimpleMemory
909665Sandreas.hansson@arm.comTestMemClass = Simulation.setMemClass(options)
919665Sandreas.hansson@arm.com
922995SN/Aif options.benchmark:
933304Sstever@eecs.umich.edu    try:
943304Sstever@eecs.umich.edu        bm = Benchmarks[options.benchmark]
953304Sstever@eecs.umich.edu    except KeyError:
962995SN/A        print "Error benchmark %s has not been defined." % options.benchmark
972995SN/A        print "Valid benchmarks are: %s" % DefinedBenchmarks
982995SN/A        sys.exit(1)
992917SN/Aelse:
1002995SN/A    if options.dual:
1018956Sjayneel@cs.wisc.edu        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
1022995SN/A    else:
1038956Sjayneel@cs.wisc.edu        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
1043304Sstever@eecs.umich.edu
1056135Sgblack@eecs.umich.edunp = options.num_cpus
1066135Sgblack@eecs.umich.edu
1076654Snate@binkert.orgif buildEnv['TARGET_ISA'] == "alpha":
1089665Sandreas.hansson@arm.com    test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0])
1096654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "mips":
1109665Sandreas.hansson@arm.com    test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0])
1116654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "sparc":
1129665Sandreas.hansson@arm.com    test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0])
1136654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "x86":
1149665Sandreas.hansson@arm.com    test_sys = makeLinuxX86System(test_mem_mode, TestMemClass,
1159665Sandreas.hansson@arm.com                                  options.num_cpus, bm[0])
1167586SAli.Saidi@arm.comelif buildEnv['TARGET_ISA'] == "arm":
1179665Sandreas.hansson@arm.com    test_sys = makeArmSystem(test_mem_mode, options.machine_type,
1189665Sandreas.hansson@arm.com                             TestMemClass, bm[0], options.dtb_filename,
1199665Sandreas.hansson@arm.com                             bare_metal=options.bare_metal)
1203819Shsul@eecs.umich.eduelse:
1219059Snilay@cs.wisc.edu    fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
1223819Shsul@eecs.umich.edu
1239790Sakash.bagdia@arm.comtest_sys.clock = options.sys_clock
1249790Sakash.bagdia@arm.com
1253873Sbinkertn@umich.eduif options.kernel is not None:
1263873Sbinkertn@umich.edu    test_sys.kernel = binary(options.kernel)
1273873Sbinkertn@umich.edu
1283873Sbinkertn@umich.eduif options.script is not None:
1293873Sbinkertn@umich.edu    test_sys.readfile = options.script
1303873Sbinkertn@umich.edu
1318659SAli.Saidi@ARM.comtest_sys.init_param = options.init_param
1328659SAli.Saidi@ARM.com
1336995Sgblack@eecs.umich.edutest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
1343668Srdreslin@umich.edu
1359653SAndreas.Sandberg@ARM.comif is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
1369653SAndreas.Sandberg@ARM.com    test_sys.vm = KvmVM()
1379653SAndreas.Sandberg@ARM.com
1386636Ssteve.reinhardt@amd.comif options.caches or options.l2cache:
1399788Sakash.bagdia@arm.com    # By default the IOCache runs at the system clock
1409788Sakash.bagdia@arm.com    test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
1418839Sandreas.hansson@arm.com    test_sys.iocache.cpu_side = test_sys.iobus.master
1428839Sandreas.hansson@arm.com    test_sys.iocache.mem_side = test_sys.membus.slave
1438713Sandreas.hansson@arm.comelse:
1449408Sandreas.hansson@arm.com    test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
1458839Sandreas.hansson@arm.com    test_sys.iobridge.slave = test_sys.iobus.master
1468839Sandreas.hansson@arm.com    test_sys.iobridge.master = test_sys.membus.slave
1475142Ssaidi@eecs.umich.edu
1488926Sandreas.hansson@arm.com# Sanity check
1499317Sandreas.hansson@arm.comif options.fastmem:
1509317Sandreas.hansson@arm.com    if TestCPUClass != AtomicSimpleCPU:
1519317Sandreas.hansson@arm.com        fatal("Fastmem can only be used with atomic CPU!")
1529317Sandreas.hansson@arm.com    if (options.caches or options.l2cache):
1539317Sandreas.hansson@arm.com        fatal("You cannot use fastmem in combination with caches!")
1548926Sandreas.hansson@arm.com
1553312Sstever@eecs.umich.edufor i in xrange(np):
1564968Sacolyte@umich.edu    if options.fastmem:
1578926Sandreas.hansson@arm.com        test_sys.cpu[i].fastmem = True
1588887Sgeoffrey.blake@arm.com    if options.checker:
1598887Sgeoffrey.blake@arm.com        test_sys.cpu[i].addCheckerCpu()
1609384SAndreas.Sandberg@arm.com    test_sys.cpu[i].createThreads()
1618887Sgeoffrey.blake@arm.com
1628887Sgeoffrey.blake@arm.comCacheConfig.config_cache(options, test_sys)
1634968Sacolyte@umich.edu
1643005Sstever@eecs.umich.eduif len(bm) == 2:
1656654Snate@binkert.org    if buildEnv['TARGET_ISA'] == 'alpha':
1669665Sandreas.hansson@arm.com        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1])
1676654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'mips':
1689665Sandreas.hansson@arm.com        drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1])
1696654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'sparc':
1709665Sandreas.hansson@arm.com        drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1])
1716654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'x86':
1729665Sandreas.hansson@arm.com        drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1])
1737586SAli.Saidi@arm.com    elif buildEnv['TARGET_ISA'] == 'arm':
1749665Sandreas.hansson@arm.com        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
1759665Sandreas.hansson@arm.com                                  DriveMemClass, bm[1])
1768661SAli.Saidi@ARM.com
1779790Sakash.bagdia@arm.com    drive_sys.clock = options.sys_clock
1789790Sakash.bagdia@arm.com
1793322Shsul@eecs.umich.edu    drive_sys.cpu = DriveCPUClass(cpu_id=0)
1809384SAndreas.Sandberg@arm.com    drive_sys.cpu.createThreads()
1818863Snilay@cs.wisc.edu    drive_sys.cpu.createInterruptController()
1827876Sgblack@eecs.umich.edu    drive_sys.cpu.connectAllPorts(drive_sys.membus)
1834968Sacolyte@umich.edu    if options.fastmem:
1848926Sandreas.hansson@arm.com        drive_sys.cpu.fastmem = True
1854837Ssaidi@eecs.umich.edu    if options.kernel is not None:
1864837Ssaidi@eecs.umich.edu        drive_sys.kernel = binary(options.kernel)
1879408Sandreas.hansson@arm.com
1889653SAndreas.Sandberg@ARM.com    if is_kvm_cpu(DriveCPUClass):
1899653SAndreas.Sandberg@ARM.com        drive_sys.vm = KvmVM()
1909653SAndreas.Sandberg@ARM.com
1919164Sandreas.hansson@arm.com    drive_sys.iobridge = Bridge(delay='50ns',
1929408Sandreas.hansson@arm.com                                ranges = drive_sys.mem_ranges)
1938845Sandreas.hansson@arm.com    drive_sys.iobridge.slave = drive_sys.iobus.master
1948845Sandreas.hansson@arm.com    drive_sys.iobridge.master = drive_sys.membus.slave
1954837Ssaidi@eecs.umich.edu
1968659SAli.Saidi@ARM.com    drive_sys.init_param = options.init_param
1978801Sgblack@eecs.umich.edu    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
1983005Sstever@eecs.umich.eduelif len(bm) == 1:
1998801Sgblack@eecs.umich.edu    root = Root(full_system=True, system=test_sys)
2003005Sstever@eecs.umich.eduelse:
2013005Sstever@eecs.umich.edu    print "Error I don't know how to create more than 2 systems."
2023005Sstever@eecs.umich.edu    sys.exit(1)
2032566SN/A
2047861Sgblack@eecs.umich.eduif options.timesync:
2057861Sgblack@eecs.umich.edu    root.time_sync_enable = True
2067861Sgblack@eecs.umich.edu
2078635Schris.emmons@arm.comif options.frame_capture:
2088635Schris.emmons@arm.com    VncServer.frame_capture = True
2098635Schris.emmons@arm.com
2109061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options)
2113481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass)
212