fs.py revision 9408
12SN/A# Copyright (c) 2010-2012 ARM Limited 21762SN/A# All rights reserved. 32SN/A# 42SN/A# The license below extends only to copyright in the software and shall 52SN/A# not be construed as granting a license to any other intellectual 62SN/A# property including but not limited to intellectual property relating 72SN/A# to a hardware implementation of the functionality of the software 82SN/A# licensed hereunder. You may use the software subject to the license 92SN/A# terms below provided that you ensure that this notice is replicated 102SN/A# unmodified and in its entirety in all distributions of the software, 112SN/A# modified or unmodified, in source code or in binary form. 122SN/A# 132SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 142SN/A# All rights reserved. 152SN/A# 162SN/A# Redistribution and use in source and binary forms, with or without 172SN/A# modification, are permitted provided that the following conditions are 182SN/A# met: redistributions of source code must retain the above copyright 192SN/A# notice, this list of conditions and the following disclaimer; 202SN/A# redistributions in binary form must reproduce the above copyright 212SN/A# notice, this list of conditions and the following disclaimer in the 222SN/A# documentation and/or other materials provided with the distribution; 232SN/A# neither the name of the copyright holders nor the names of its 242SN/A# contributors may be used to endorse or promote products derived from 252SN/A# this software without specific prior written permission. 262SN/A# 272665SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282665SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3411263Sandreas.sandberg@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36146SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382SN/A# 392SN/A# Authors: Ali Saidi 402SN/A 4112334Sgabeblack@google.comimport optparse 42146SN/Aimport sys 438232SN/A 448232SN/Aimport m5 4511263Sandreas.sandberg@arm.comfrom m5.defines import buildEnv 4611263Sandreas.sandberg@arm.comfrom m5.objects import * 4711263Sandreas.sandberg@arm.comfrom m5.util import addToPath, fatal 484762SN/A 494167SN/AaddToPath('../common') 502SN/A 512SN/Afrom FSConfig import * 522SN/Afrom SysPaths import * 534981SN/Afrom Benchmarks import * 5413766Sgabeblack@google.comimport Simulation 5512130Sspwilson2@wisc.eduimport CacheConfig 5612130Sspwilson2@wisc.edufrom Caches import * 571634SN/Aimport Options 581634SN/A 592SN/Aparser = optparse.OptionParser() 602SN/AOptions.addCommonOptions(parser) 612SN/AOptions.addFSOptions(parser) 622SN/A 632SN/A(options, args) = parser.parse_args() 642SN/A 652SN/Aif args: 662SN/A print "Error: script doesn't take any positional arguments" 672SN/A sys.exit(1) 682SN/A 692SN/A# driver system CPU is always simple... note this is an assignment of 702SN/A# a class, not an instance. 712SN/ADriveCPUClass = AtomicSimpleCPU 722SN/Adrive_mem_mode = 'atomic' 732SN/A 742SN/A# system under test can be any CPU 752SN/A(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 762SN/A 772SN/ATestCPUClass.clock = options.clock 782SN/ADriveCPUClass.clock = options.clock 792SN/A 802SN/Aif options.benchmark: 812SN/A try: 822SN/A bm = Benchmarks[options.benchmark] 832SN/A except KeyError: 844981SN/A print "Error benchmark %s has not been defined." % options.benchmark 854981SN/A print "Valid benchmarks are: %s" % DefinedBenchmarks 864981SN/A sys.exit(1) 874981SN/Aelse: 884981SN/A if options.dual: 892SN/A bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 902SN/A else: 912566SN/A bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 922SN/A 932SN/Anp = options.num_cpus 947823SN/A 952SN/Aif buildEnv['TARGET_ISA'] == "alpha": 962SN/A test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 972SN/Aelif buildEnv['TARGET_ISA'] == "mips": 982SN/A test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 992SN/Aelif buildEnv['TARGET_ISA'] == "sparc": 1002SN/A test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1012SN/Aelif buildEnv['TARGET_ISA'] == "x86": 1022SN/A test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 10311701Smichael.lebeane@amd.comelif buildEnv['TARGET_ISA'] == "arm": 1042SN/A test_sys = makeArmSystem(test_mem_mode, 1051634SN/A options.machine_type, bm[0], 1067823SN/A bare_metal=options.bare_metal) 1072SN/Aelse: 1082SN/A fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1092SN/A 1102SN/Aif options.kernel is not None: 1114762SN/A test_sys.kernel = binary(options.kernel) 1124762SN/A 1132SN/Aif options.script is not None: 1144981SN/A test_sys.readfile = options.script 1152SN/A 116test_sys.init_param = options.init_param 117 118test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 119 120if options.caches or options.l2cache: 121 test_sys.iocache = IOCache(clock = '1GHz', 122 addr_ranges = test_sys.mem_ranges) 123 test_sys.iocache.cpu_side = test_sys.iobus.master 124 test_sys.iocache.mem_side = test_sys.membus.slave 125else: 126 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 127 test_sys.iobridge.slave = test_sys.iobus.master 128 test_sys.iobridge.master = test_sys.membus.slave 129 130# Sanity check 131if options.fastmem: 132 if TestCPUClass != AtomicSimpleCPU: 133 fatal("Fastmem can only be used with atomic CPU!") 134 if (options.caches or options.l2cache): 135 fatal("You cannot use fastmem in combination with caches!") 136 137for i in xrange(np): 138 if options.fastmem: 139 test_sys.cpu[i].fastmem = True 140 if options.checker: 141 test_sys.cpu[i].addCheckerCpu() 142 test_sys.cpu[i].createThreads() 143 144CacheConfig.config_cache(options, test_sys) 145 146if len(bm) == 2: 147 if buildEnv['TARGET_ISA'] == 'alpha': 148 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 149 elif buildEnv['TARGET_ISA'] == 'mips': 150 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 151 elif buildEnv['TARGET_ISA'] == 'sparc': 152 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 153 elif buildEnv['TARGET_ISA'] == 'x86': 154 drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 155 elif buildEnv['TARGET_ISA'] == 'arm': 156 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 157 158 drive_sys.cpu = DriveCPUClass(cpu_id=0) 159 drive_sys.cpu.createThreads() 160 drive_sys.cpu.createInterruptController() 161 drive_sys.cpu.connectAllPorts(drive_sys.membus) 162 if options.fastmem: 163 drive_sys.cpu.fastmem = True 164 if options.kernel is not None: 165 drive_sys.kernel = binary(options.kernel) 166 167 drive_sys.iobridge = Bridge(delay='50ns', 168 ranges = drive_sys.mem_ranges) 169 drive_sys.iobridge.slave = drive_sys.iobus.master 170 drive_sys.iobridge.master = drive_sys.membus.slave 171 172 drive_sys.init_param = options.init_param 173 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 174elif len(bm) == 1: 175 root = Root(full_system=True, system=test_sys) 176else: 177 print "Error I don't know how to create more than 2 systems." 178 sys.exit(1) 179 180if options.timesync: 181 root.time_sync_enable = True 182 183if options.frame_capture: 184 VncServer.frame_capture = True 185 186Simulation.setWorkCountOptions(test_sys, options) 187Simulation.run(options, root, test_sys, FutureClass) 188