fs.py revision 9164
18926Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 133970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 143005Sstever@eecs.umich.edu# All rights reserved. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253005Sstever@eecs.umich.edu# this software without specific prior written permission. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383005Sstever@eecs.umich.edu# 393005Sstever@eecs.umich.edu# Authors: Ali Saidi 403005Sstever@eecs.umich.edu 416654Snate@binkert.orgimport optparse 426654Snate@binkert.orgimport sys 432889SN/A 442710SN/Aimport m5 456654Snate@binkert.orgfrom m5.defines import buildEnv 466654Snate@binkert.orgfrom m5.objects import * 476654Snate@binkert.orgfrom m5.util import addToPath, fatal 485457Ssaidi@eecs.umich.edu 496654Snate@binkert.orgaddToPath('../common') 506654Snate@binkert.org 512934SN/Afrom FSConfig import * 522549SN/Afrom SysPaths import * 532995SN/Afrom Benchmarks import * 543395Shsul@eecs.umich.eduimport Simulation 556981SLisa.Hsu@amd.comimport CacheConfig 563448Shsul@eecs.umich.edufrom Caches import * 578920Snilay@cs.wisc.eduimport Options 583444Sktlim@umich.edu 592889SN/Aparser = optparse.OptionParser() 608920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 618920Snilay@cs.wisc.eduOptions.addFSOptions(parser) 623322Shsul@eecs.umich.edu 632710SN/A(options, args) = parser.parse_args() 642710SN/A 652710SN/Aif args: 662710SN/A print "Error: script doesn't take any positional arguments" 672710SN/A sys.exit(1) 682710SN/A 693322Shsul@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of 703304Sstever@eecs.umich.edu# a class, not an instance. 713322Shsul@eecs.umich.eduDriveCPUClass = AtomicSimpleCPU 723322Shsul@eecs.umich.edudrive_mem_mode = 'atomic' 733304Sstever@eecs.umich.edu 743481Shsul@eecs.umich.edu# system under test can be any CPU 753481Shsul@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 762566SN/A 779129Sandreas.hansson@arm.comTestCPUClass.clock = options.clock 789129Sandreas.hansson@arm.comDriveCPUClass.clock = options.clock 792995SN/A 802995SN/Aif options.benchmark: 813304Sstever@eecs.umich.edu try: 823304Sstever@eecs.umich.edu bm = Benchmarks[options.benchmark] 833304Sstever@eecs.umich.edu except KeyError: 842995SN/A print "Error benchmark %s has not been defined." % options.benchmark 852995SN/A print "Valid benchmarks are: %s" % DefinedBenchmarks 862995SN/A sys.exit(1) 872917SN/Aelse: 882995SN/A if options.dual: 898956Sjayneel@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 902995SN/A else: 918956Sjayneel@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 923304Sstever@eecs.umich.edu 936135Sgblack@eecs.umich.edunp = options.num_cpus 946135Sgblack@eecs.umich.edu 956654Snate@binkert.orgif buildEnv['TARGET_ISA'] == "alpha": 963819Shsul@eecs.umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 976654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "mips": 985222Sksewell@umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 996654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "sparc": 1003819Shsul@eecs.umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1016654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "x86": 1027925Sgblack@eecs.umich.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 1037586SAli.Saidi@arm.comelif buildEnv['TARGET_ISA'] == "arm": 1048061SAli.Saidi@ARM.com test_sys = makeArmSystem(test_mem_mode, 1058061SAli.Saidi@ARM.com options.machine_type, bm[0], 1068061SAli.Saidi@ARM.com bare_metal=options.bare_metal) 1073819Shsul@eecs.umich.eduelse: 1089059Snilay@cs.wisc.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1093819Shsul@eecs.umich.edu 1103873Sbinkertn@umich.eduif options.kernel is not None: 1113873Sbinkertn@umich.edu test_sys.kernel = binary(options.kernel) 1123873Sbinkertn@umich.edu 1133873Sbinkertn@umich.eduif options.script is not None: 1143873Sbinkertn@umich.edu test_sys.readfile = options.script 1153873Sbinkertn@umich.edu 1168659SAli.Saidi@ARM.comtest_sys.init_param = options.init_param 1178659SAli.Saidi@ARM.com 1186995Sgblack@eecs.umich.edutest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 1193668Srdreslin@umich.edu 1208713Sandreas.hansson@arm.comif bm[0]: 1218713Sandreas.hansson@arm.com mem_size = bm[0].mem() 1228713Sandreas.hansson@arm.comelse: 1238713Sandreas.hansson@arm.com mem_size = SysConfig().mem() 1246636Ssteve.reinhardt@amd.comif options.caches or options.l2cache: 1258894Ssaidi@eecs.umich.edu test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range]) 1268839Sandreas.hansson@arm.com test_sys.iocache.cpu_side = test_sys.iobus.master 1278839Sandreas.hansson@arm.com test_sys.iocache.mem_side = test_sys.membus.slave 1288713Sandreas.hansson@arm.comelse: 1299164Sandreas.hansson@arm.com test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range]) 1308839Sandreas.hansson@arm.com test_sys.iobridge.slave = test_sys.iobus.master 1318839Sandreas.hansson@arm.com test_sys.iobridge.master = test_sys.membus.slave 1325142Ssaidi@eecs.umich.edu 1338926Sandreas.hansson@arm.com# Sanity check 1348926Sandreas.hansson@arm.comif options.fastmem and (options.caches or options.l2cache): 1358926Sandreas.hansson@arm.com fatal("You cannot use fastmem in combination with caches!") 1368926Sandreas.hansson@arm.com 1373312Sstever@eecs.umich.edufor i in xrange(np): 1384968Sacolyte@umich.edu if options.fastmem: 1398926Sandreas.hansson@arm.com test_sys.cpu[i].fastmem = True 1408887Sgeoffrey.blake@arm.com if options.checker: 1418887Sgeoffrey.blake@arm.com test_sys.cpu[i].addCheckerCpu() 1428887Sgeoffrey.blake@arm.com 1438887Sgeoffrey.blake@arm.comCacheConfig.config_cache(options, test_sys) 1444968Sacolyte@umich.edu 1453005Sstever@eecs.umich.eduif len(bm) == 2: 1466654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'alpha': 1473819Shsul@eecs.umich.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 1486654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 1495222Sksewell@umich.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 1506654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'sparc': 1513819Shsul@eecs.umich.edu drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 1526654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 1536135Sgblack@eecs.umich.edu drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 1547586SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 1558661SAli.Saidi@ARM.com drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 1568661SAli.Saidi@ARM.com 1573322Shsul@eecs.umich.edu drive_sys.cpu = DriveCPUClass(cpu_id=0) 1588863Snilay@cs.wisc.edu drive_sys.cpu.createInterruptController() 1597876Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 1604968Sacolyte@umich.edu if options.fastmem: 1618926Sandreas.hansson@arm.com drive_sys.cpu.fastmem = True 1624837Ssaidi@eecs.umich.edu if options.kernel is not None: 1634837Ssaidi@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 1649164Sandreas.hansson@arm.com drive_sys.iobridge = Bridge(delay='50ns', 1659164Sandreas.hansson@arm.com ranges = [drive_sys.physmem.range]) 1668845Sandreas.hansson@arm.com drive_sys.iobridge.slave = drive_sys.iobus.master 1678845Sandreas.hansson@arm.com drive_sys.iobridge.master = drive_sys.membus.slave 1684837Ssaidi@eecs.umich.edu 1698659SAli.Saidi@ARM.com drive_sys.init_param = options.init_param 1708801Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 1713005Sstever@eecs.umich.eduelif len(bm) == 1: 1728801Sgblack@eecs.umich.edu root = Root(full_system=True, system=test_sys) 1733005Sstever@eecs.umich.eduelse: 1743005Sstever@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 1753005Sstever@eecs.umich.edu sys.exit(1) 1762566SN/A 1777861Sgblack@eecs.umich.eduif options.timesync: 1787861Sgblack@eecs.umich.edu root.time_sync_enable = True 1797861Sgblack@eecs.umich.edu 1808635Schris.emmons@arm.comif options.frame_capture: 1818635Schris.emmons@arm.com VncServer.frame_capture = True 1828635Schris.emmons@arm.com 1839061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options) 1843481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 185