fs.py revision 5222
13970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 23005Sstever@eecs.umich.edu# All rights reserved. 33005Sstever@eecs.umich.edu# 43005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 63005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133005Sstever@eecs.umich.edu# this software without specific prior written permission. 143005Sstever@eecs.umich.edu# 153005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# Authors: Ali Saidi 283005Sstever@eecs.umich.edu 292889SN/Aimport optparse, os, sys 302889SN/A 312710SN/Aimport m5 322710SN/Afrom m5.objects import * 332934SN/Am5.AddToPath('../common') 342934SN/Afrom FSConfig import * 352549SN/Afrom SysPaths import * 362995SN/Afrom Benchmarks import * 373395Shsul@eecs.umich.eduimport Simulation 383448Shsul@eecs.umich.edufrom Caches import * 392549SN/A 403088Sstever@eecs.umich.eduif not m5.build_env['FULL_SYSTEM']: 413088Sstever@eecs.umich.edu m5.panic("This script requires full-system mode (ALPHA_FS).") 423088Sstever@eecs.umich.edu 433444Sktlim@umich.edu# Get paths we might need. It's expected this file is in m5/configs/example. 443444Sktlim@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__)) 453444Sktlim@umich.educonfig_root = os.path.dirname(config_path) 463444Sktlim@umich.edu 472889SN/Aparser = optparse.OptionParser() 482710SN/A 493873Sbinkertn@umich.edu# System options 503873Sbinkertn@umich.eduparser.add_option("--kernel", action="store", type="string") 513873Sbinkertn@umich.eduparser.add_option("--script", action="store", type="string") 523873Sbinkertn@umich.edu 533322Shsul@eecs.umich.edu# Benchmark options 542995SN/Aparser.add_option("--dual", action="store_true", 552995SN/A help="Simulate two systems attached with an ethernet link") 562995SN/Aparser.add_option("-b", "--benchmark", action="store", type="string", 572995SN/A dest="benchmark", 582995SN/A help="Specify the benchmark to run. Available benchmarks: %s"\ 593143Shsul@eecs.umich.edu % DefinedBenchmarks) 603322Shsul@eecs.umich.edu 613322Shsul@eecs.umich.edu# Metafile options 623025Ssaidi@eecs.umich.eduparser.add_option("--etherdump", action="store", type="string", dest="etherdump", 633143Shsul@eecs.umich.edu help="Specify the filename to dump a pcap capture of the" \ 643143Shsul@eecs.umich.edu "ethernet traffic") 653322Shsul@eecs.umich.edu 663444Sktlim@umich.eduexecfile(os.path.join(config_root, "common", "Options.py")) 673322Shsul@eecs.umich.edu 682710SN/A(options, args) = parser.parse_args() 692710SN/A 702710SN/Aif args: 712710SN/A print "Error: script doesn't take any positional arguments" 722710SN/A sys.exit(1) 732710SN/A 743322Shsul@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of 753304Sstever@eecs.umich.edu# a class, not an instance. 763322Shsul@eecs.umich.eduDriveCPUClass = AtomicSimpleCPU 773322Shsul@eecs.umich.edudrive_mem_mode = 'atomic' 783304Sstever@eecs.umich.edu 793481Shsul@eecs.umich.edu# system under test can be any CPU 803481Shsul@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 812566SN/A 823322Shsul@eecs.umich.eduTestCPUClass.clock = '2GHz' 833322Shsul@eecs.umich.eduDriveCPUClass.clock = '2GHz' 842995SN/A 852995SN/Aif options.benchmark: 863304Sstever@eecs.umich.edu try: 873304Sstever@eecs.umich.edu bm = Benchmarks[options.benchmark] 883304Sstever@eecs.umich.edu except KeyError: 892995SN/A print "Error benchmark %s has not been defined." % options.benchmark 902995SN/A print "Valid benchmarks are: %s" % DefinedBenchmarks 912995SN/A sys.exit(1) 922917SN/Aelse: 932995SN/A if options.dual: 943304Sstever@eecs.umich.edu bm = [SysConfig(), SysConfig()] 952995SN/A else: 963304Sstever@eecs.umich.edu bm = [SysConfig()] 973304Sstever@eecs.umich.edu 983819Shsul@eecs.umich.eduif m5.build_env['TARGET_ISA'] == "alpha": 993819Shsul@eecs.umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 1005222Sksewell@umich.eduelif m5.build_env['TARGET_ISA'] == "mips": 1015222Sksewell@umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 1023819Shsul@eecs.umich.eduelif m5.build_env['TARGET_ISA'] == "sparc": 1033819Shsul@eecs.umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1045133Sgblack@eecs.umich.eduelif m5.build_env['TARGET_ISA'] == "x86": 1055133Sgblack@eecs.umich.edu test_sys = makeX86System(test_mem_mode, bm[0]) 1063819Shsul@eecs.umich.eduelse: 1073819Shsul@eecs.umich.edu m5.panic("incapable of building non-alpha or non-sparc full system!") 1083819Shsul@eecs.umich.edu 1093873Sbinkertn@umich.eduif options.kernel is not None: 1103873Sbinkertn@umich.edu test_sys.kernel = binary(options.kernel) 1113873Sbinkertn@umich.edu 1123873Sbinkertn@umich.eduif options.script is not None: 1133873Sbinkertn@umich.edu test_sys.readfile = options.script 1143873Sbinkertn@umich.edu 1153312Sstever@eecs.umich.edunp = options.num_cpus 1163668Srdreslin@umich.edu 1173668Srdreslin@umich.eduif options.l2cache: 1183668Srdreslin@umich.edu test_sys.l2 = L2Cache(size = '2MB') 1193668Srdreslin@umich.edu test_sys.tol2bus = Bus() 1203668Srdreslin@umich.edu test_sys.l2.cpu_side = test_sys.tol2bus.port 1213668Srdreslin@umich.edu test_sys.l2.mem_side = test_sys.membus.port 1223668Srdreslin@umich.edu 1233322Shsul@eecs.umich.edutest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 1245142Ssaidi@eecs.umich.edu 1255142Ssaidi@eecs.umich.eduif options.caches: 1265142Ssaidi@eecs.umich.edu test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 1275142Ssaidi@eecs.umich.edu test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] 1285142Ssaidi@eecs.umich.edu test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)], 1295142Ssaidi@eecs.umich.edu cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]) 1305142Ssaidi@eecs.umich.edu test_sys.iocache.cpu_side = test_sys.iobus.port 1315142Ssaidi@eecs.umich.edu test_sys.iocache.mem_side = test_sys.membus.port 1325142Ssaidi@eecs.umich.edu 1333312Sstever@eecs.umich.edufor i in xrange(np): 1343514Sktlim@umich.edu if options.caches: 1353395Shsul@eecs.umich.edu test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 1363448Shsul@eecs.umich.edu L1Cache(size = '64kB')) 1373668Srdreslin@umich.edu if options.l2cache: 1383668Srdreslin@umich.edu test_sys.cpu[i].connectMemPorts(test_sys.tol2bus) 1393668Srdreslin@umich.edu else: 1403668Srdreslin@umich.edu test_sys.cpu[i].connectMemPorts(test_sys.membus) 1413005Sstever@eecs.umich.edu 1424968Sacolyte@umich.edu if options.fastmem: 1434968Sacolyte@umich.edu test_sys.cpu[i].physmem_port = test_sys.physmem.port 1444968Sacolyte@umich.edu 1455222Sksewell@umich.eduif m5.build_env['TARGET_ISA'] == 'mips': 1465222Sksewell@umich.edu #CP0 Configuration 1475222Sksewell@umich.edu TestCPUClass.CP0_PRId_CompanyOptions = 0 1485222Sksewell@umich.edu TestCPUClass.CP0_PRId_CompanyID = 1 1495222Sksewell@umich.edu TestCPUClass.CP0_PRId_ProcessorID = 147 1505222Sksewell@umich.edu TestCPUClass.CP0_PRId_Revision = 0 1515222Sksewell@umich.edu 1525222Sksewell@umich.edu #CP0 Interrupt Control 1535222Sksewell@umich.edu TestCPUClass.CP0_IntCtl_IPTI = 7 1545222Sksewell@umich.edu TestCPUClass.CP0_IntCtl_IPPCI = 7 1555222Sksewell@umich.edu 1565222Sksewell@umich.edu # Config Register 1575222Sksewell@umich.edu #TestCPUClass.CP0_Config_K23 = 0 # Since TLB 1585222Sksewell@umich.edu #TestCPUClass.CP0_Config_KU = 0 # Since TLB 1595222Sksewell@umich.edu TestCPUClass.CP0_Config_BE = 0 # Little Endian 1605222Sksewell@umich.edu TestCPUClass.CP0_Config_AR = 1 # Architecture Revision 2 1615222Sksewell@umich.edu TestCPUClass.CP0_Config_AT = 0 # MIPS32 1625222Sksewell@umich.edu TestCPUClass.CP0_Config_MT = 1 # TLB MMU 1635222Sksewell@umich.edu #TestCPUClass.CP0_Config_K0 = 2 # Uncached 1645222Sksewell@umich.edu 1655222Sksewell@umich.edu #Config 1 Register 1665222Sksewell@umich.edu TestCPUClass.CP0_Config1_M = 1 # Config2 Implemented 1675222Sksewell@umich.edu TestCPUClass.CP0_Config1_MMU = 63 # TLB Size 1685222Sksewell@umich.edu # ***VERY IMPORTANT*** 1695222Sksewell@umich.edu # Remember to modify CP0_Config1 according to cache specs 1705222Sksewell@umich.edu # Examine file ../common/Cache.py 1715222Sksewell@umich.edu TestCPUClass.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 1725222Sksewell@umich.edu TestCPUClass.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 1735222Sksewell@umich.edu TestCPUClass.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 1745222Sksewell@umich.edu TestCPUClass.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 1755222Sksewell@umich.edu TestCPUClass.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 1765222Sksewell@umich.edu TestCPUClass.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 1775222Sksewell@umich.edu TestCPUClass.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 1785222Sksewell@umich.edu TestCPUClass.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 1795222Sksewell@umich.edu TestCPUClass.CP0_Config1_PC = 1 # Performance Counters Implemented 1805222Sksewell@umich.edu TestCPUClass.CP0_Config1_WR = 0 # Watch Registers Implemented 1815222Sksewell@umich.edu TestCPUClass.CP0_Config1_CA = 0 # Mips16e NOT implemented 1825222Sksewell@umich.edu TestCPUClass.CP0_Config1_EP = 0 # EJTag Not Implemented 1835222Sksewell@umich.edu TestCPUClass.CP0_Config1_FP = 0 # FPU Implemented 1845222Sksewell@umich.edu 1855222Sksewell@umich.edu #Config 2 Register 1865222Sksewell@umich.edu TestCPUClass.CP0_Config2_M = 1 # Config3 Implemented 1875222Sksewell@umich.edu TestCPUClass.CP0_Config2_TU = 0 # Tertiary Cache Control 1885222Sksewell@umich.edu TestCPUClass.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 1895222Sksewell@umich.edu TestCPUClass.CP0_Config2_TL = 0 # Tertiary Cache Line Size 1905222Sksewell@umich.edu TestCPUClass.CP0_Config2_TA = 0 # Tertiary Cache Associativity 1915222Sksewell@umich.edu TestCPUClass.CP0_Config2_SU = 0 # Secondary Cache Control 1925222Sksewell@umich.edu TestCPUClass.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 1935222Sksewell@umich.edu TestCPUClass.CP0_Config2_SL = 0 # Secondary Cache Line Size 1945222Sksewell@umich.edu TestCPUClass.CP0_Config2_SA = 0 # Secondary Cache Associativity 1955222Sksewell@umich.edu 1965222Sksewell@umich.edu 1975222Sksewell@umich.edu #Config 3 Register 1985222Sksewell@umich.edu TestCPUClass.CP0_Config3_M = 0 # Config4 Not Implemented 1995222Sksewell@umich.edu TestCPUClass.CP0_Config3_DSPP = 1 # DSP ASE Present 2005222Sksewell@umich.edu TestCPUClass.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 2015222Sksewell@umich.edu TestCPUClass.CP0_Config3_VEIC = 0 # EIC Supported 2025222Sksewell@umich.edu TestCPUClass.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 2035222Sksewell@umich.edu TestCPUClass.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 2045222Sksewell@umich.edu TestCPUClass.CP0_Config3_MT = 0 # MT Not present 2055222Sksewell@umich.edu TestCPUClass.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 2065222Sksewell@umich.edu TestCPUClass.CP0_Config3_TL = 0 # TraceLogic Not implemented 2075222Sksewell@umich.edu 2085222Sksewell@umich.edu #SRS Ctl - HSS 2095222Sksewell@umich.edu TestCPUClass.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 2105222Sksewell@umich.edu 2115222Sksewell@umich.edu 2125222Sksewell@umich.edu #TestCPUClass.tlb = TLB() 2135222Sksewell@umich.edu #TestCPUClass.UnifiedTLB = 1 2145222Sksewell@umich.edu 2153005Sstever@eecs.umich.eduif len(bm) == 2: 2163819Shsul@eecs.umich.edu if m5.build_env['TARGET_ISA'] == 'alpha': 2173819Shsul@eecs.umich.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 2185222Sksewell@umich.edu elif m5.build_env['TARGET_ISA'] == 'mips': 2195222Sksewell@umich.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 2203819Shsul@eecs.umich.edu elif m5.build_env['TARGET_ISA'] == 'sparc': 2213819Shsul@eecs.umich.edu drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 2225133Sgblack@eecs.umich.edu elif m5.build.env['TARGET_ISA'] == 'x86': 2235133Sgblack@eecs.umich.edu drive_sys = makeX86System(drive_mem_mode, bm[1]) 2243322Shsul@eecs.umich.edu drive_sys.cpu = DriveCPUClass(cpu_id=0) 2253322Shsul@eecs.umich.edu drive_sys.cpu.connectMemPorts(drive_sys.membus) 2264968Sacolyte@umich.edu if options.fastmem: 2274968Sacolyte@umich.edu drive_sys.cpu.physmem_port = drive_sys.physmem.port 2284837Ssaidi@eecs.umich.edu if options.kernel is not None: 2294837Ssaidi@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2304837Ssaidi@eecs.umich.edu 2313322Shsul@eecs.umich.edu root = makeDualRoot(test_sys, drive_sys, options.etherdump) 2323005Sstever@eecs.umich.eduelif len(bm) == 1: 2334167Sbinkertn@umich.edu root = Root(system=test_sys) 2343005Sstever@eecs.umich.eduelse: 2353005Sstever@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 2363005Sstever@eecs.umich.edu sys.exit(1) 2372566SN/A 2383481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 239