fs.py revision 3819
13005Sstever@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
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33005Sstever@eecs.umich.edu#
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53005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
63005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
73005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
83005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
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123005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
133005Sstever@eecs.umich.edu# this software without specific prior written permission.
143005Sstever@eecs.umich.edu#
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263005Sstever@eecs.umich.edu#
273005Sstever@eecs.umich.edu# Authors: Ali Saidi
283005Sstever@eecs.umich.edu
292889SN/Aimport optparse, os, sys
302889SN/A
312710SN/Aimport m5
322710SN/Afrom m5.objects import *
332934SN/Am5.AddToPath('../common')
342934SN/Afrom FSConfig import *
352549SN/Afrom SysPaths import *
362995SN/Afrom Benchmarks import *
373395Shsul@eecs.umich.eduimport Simulation
383448Shsul@eecs.umich.edufrom Caches import *
392549SN/A
403088Sstever@eecs.umich.eduif not m5.build_env['FULL_SYSTEM']:
413088Sstever@eecs.umich.edu    m5.panic("This script requires full-system mode (ALPHA_FS).")
423088Sstever@eecs.umich.edu
433444Sktlim@umich.edu# Get paths we might need.  It's expected this file is in m5/configs/example.
443444Sktlim@umich.educonfig_path = os.path.dirname(os.path.abspath(__file__))
453444Sktlim@umich.educonfig_root = os.path.dirname(config_path)
463444Sktlim@umich.edu
472889SN/Aparser = optparse.OptionParser()
482710SN/A
493322Shsul@eecs.umich.edu# Benchmark options
503668Srdreslin@umich.eduparser.add_option("--l2cache", action="store_true")
512995SN/Aparser.add_option("--dual", action="store_true",
522995SN/A                  help="Simulate two systems attached with an ethernet link")
532995SN/Aparser.add_option("-b", "--benchmark", action="store", type="string",
542995SN/A                  dest="benchmark",
552995SN/A                  help="Specify the benchmark to run. Available benchmarks: %s"\
563143Shsul@eecs.umich.edu                  % DefinedBenchmarks)
573322Shsul@eecs.umich.edu
583322Shsul@eecs.umich.edu# Metafile options
593025Ssaidi@eecs.umich.eduparser.add_option("--etherdump", action="store", type="string", dest="etherdump",
603143Shsul@eecs.umich.edu                  help="Specify the filename to dump a pcap capture of the" \
613143Shsul@eecs.umich.edu                  "ethernet traffic")
623322Shsul@eecs.umich.edu
633444Sktlim@umich.eduexecfile(os.path.join(config_root, "common", "Options.py"))
643322Shsul@eecs.umich.edu
652710SN/A(options, args) = parser.parse_args()
662710SN/A
672710SN/Aif args:
682710SN/A    print "Error: script doesn't take any positional arguments"
692710SN/A    sys.exit(1)
702710SN/A
713322Shsul@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of
723304Sstever@eecs.umich.edu# a class, not an instance.
733322Shsul@eecs.umich.eduDriveCPUClass = AtomicSimpleCPU
743322Shsul@eecs.umich.edudrive_mem_mode = 'atomic'
753304Sstever@eecs.umich.edu
763481Shsul@eecs.umich.edu# system under test can be any CPU
773481Shsul@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
782566SN/A
793322Shsul@eecs.umich.eduTestCPUClass.clock = '2GHz'
803322Shsul@eecs.umich.eduDriveCPUClass.clock = '2GHz'
812995SN/A
822995SN/Aif options.benchmark:
833304Sstever@eecs.umich.edu    try:
843304Sstever@eecs.umich.edu        bm = Benchmarks[options.benchmark]
853304Sstever@eecs.umich.edu    except KeyError:
862995SN/A        print "Error benchmark %s has not been defined." % options.benchmark
872995SN/A        print "Valid benchmarks are: %s" % DefinedBenchmarks
882995SN/A        sys.exit(1)
892917SN/Aelse:
902995SN/A    if options.dual:
913304Sstever@eecs.umich.edu        bm = [SysConfig(), SysConfig()]
922995SN/A    else:
933304Sstever@eecs.umich.edu        bm = [SysConfig()]
943304Sstever@eecs.umich.edu
953819Shsul@eecs.umich.eduif m5.build_env['TARGET_ISA'] == "alpha":
963819Shsul@eecs.umich.edu    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
973819Shsul@eecs.umich.eduelif m5.build_env['TARGET_ISA'] == "sparc":
983819Shsul@eecs.umich.edu    test_sys = makeSparcSystem(test_mem_mode, bm[0])
993819Shsul@eecs.umich.eduelse:
1003819Shsul@eecs.umich.edu    m5.panic("incapable of building non-alpha or non-sparc full system!")
1013819Shsul@eecs.umich.edu
1023312Sstever@eecs.umich.edunp = options.num_cpus
1033668Srdreslin@umich.edu
1043668Srdreslin@umich.eduif options.l2cache:
1053668Srdreslin@umich.edu    test_sys.l2 = L2Cache(size = '2MB')
1063668Srdreslin@umich.edu    test_sys.tol2bus = Bus()
1073668Srdreslin@umich.edu    test_sys.l2.cpu_side = test_sys.tol2bus.port
1083668Srdreslin@umich.edu    test_sys.l2.mem_side = test_sys.membus.port
1093668Srdreslin@umich.edu
1103322Shsul@eecs.umich.edutest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
1113312Sstever@eecs.umich.edufor i in xrange(np):
1123514Sktlim@umich.edu    if options.caches:
1133395Shsul@eecs.umich.edu        test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
1143448Shsul@eecs.umich.edu                                                L1Cache(size = '64kB'))
1153668Srdreslin@umich.edu
1163668Srdreslin@umich.edu    if options.l2cache:
1173668Srdreslin@umich.edu        test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
1183668Srdreslin@umich.edu    else:
1193668Srdreslin@umich.edu        test_sys.cpu[i].connectMemPorts(test_sys.membus)
1203005Sstever@eecs.umich.edu
1213005Sstever@eecs.umich.eduif len(bm) == 2:
1223819Shsul@eecs.umich.edu    if m5.build_env['TARGET_ISA'] == 'alpha':
1233819Shsul@eecs.umich.edu        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
1243819Shsul@eecs.umich.edu    elif m5.build_env['TARGET_ISA'] == 'sparc':
1253819Shsul@eecs.umich.edu        drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
1263322Shsul@eecs.umich.edu    drive_sys.cpu = DriveCPUClass(cpu_id=0)
1273322Shsul@eecs.umich.edu    drive_sys.cpu.connectMemPorts(drive_sys.membus)
1283322Shsul@eecs.umich.edu    root = makeDualRoot(test_sys, drive_sys, options.etherdump)
1293005Sstever@eecs.umich.eduelif len(bm) == 1:
1303322Shsul@eecs.umich.edu    root = Root(clock = '1THz', system = test_sys)
1313005Sstever@eecs.umich.eduelse:
1323005Sstever@eecs.umich.edu    print "Error I don't know how to create more than 2 systems."
1333005Sstever@eecs.umich.edu    sys.exit(1)
1342566SN/A
1353481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass)
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