fs.py revision 2889
110259SAndrew.Bardsley@arm.comimport optparse, os, sys
210259SAndrew.Bardsley@arm.com
310259SAndrew.Bardsley@arm.comimport m5
410259SAndrew.Bardsley@arm.comfrom m5.objects import *
510259SAndrew.Bardsley@arm.comfrom SysPaths import *
610259SAndrew.Bardsley@arm.com
710259SAndrew.Bardsley@arm.comparser = optparse.OptionParser()
810259SAndrew.Bardsley@arm.com
910259SAndrew.Bardsley@arm.comparser.add_option("-t", "--timing", action="store_true")
1010259SAndrew.Bardsley@arm.com
1110259SAndrew.Bardsley@arm.com(options, args) = parser.parse_args()
1210259SAndrew.Bardsley@arm.com
1310259SAndrew.Bardsley@arm.comif args:
1410259SAndrew.Bardsley@arm.com    print "Error: script doesn't take any positional arguments"
1510259SAndrew.Bardsley@arm.com    sys.exit(1)
1610259SAndrew.Bardsley@arm.com
1710259SAndrew.Bardsley@arm.com# Base for tests is directory containing this file.
1810259SAndrew.Bardsley@arm.comtest_base = os.path.dirname(__file__)
1910259SAndrew.Bardsley@arm.com
2010259SAndrew.Bardsley@arm.comlinux_image = env.get('LINUX_IMAGE', disk('linux-latest.img'))
2110259SAndrew.Bardsley@arm.com
2210259SAndrew.Bardsley@arm.comclass IdeControllerPciData(PciConfigData):
2310259SAndrew.Bardsley@arm.com    VendorID = 0x8086
2410259SAndrew.Bardsley@arm.com    DeviceID = 0x7111
2510259SAndrew.Bardsley@arm.com    Command = 0x0
2610259SAndrew.Bardsley@arm.com    Status = 0x280
2710259SAndrew.Bardsley@arm.com    Revision = 0x0
2810259SAndrew.Bardsley@arm.com    ClassCode = 0x01
2910259SAndrew.Bardsley@arm.com    SubClassCode = 0x01
3010259SAndrew.Bardsley@arm.com    ProgIF = 0x85
3110259SAndrew.Bardsley@arm.com    BAR0 = 0x00000001
3210259SAndrew.Bardsley@arm.com    BAR1 = 0x00000001
3310259SAndrew.Bardsley@arm.com    BAR2 = 0x00000001
3410259SAndrew.Bardsley@arm.com    BAR3 = 0x00000001
3510259SAndrew.Bardsley@arm.com    BAR4 = 0x00000001
3610259SAndrew.Bardsley@arm.com    BAR5 = 0x00000001
3710259SAndrew.Bardsley@arm.com    InterruptLine = 0x1f
3810259SAndrew.Bardsley@arm.com    InterruptPin = 0x01
3910259SAndrew.Bardsley@arm.com    BAR0Size = '8B'
4010259SAndrew.Bardsley@arm.com    BAR1Size = '4B'
4110259SAndrew.Bardsley@arm.com    BAR2Size = '8B'
4210259SAndrew.Bardsley@arm.com    BAR3Size = '4B'
4310259SAndrew.Bardsley@arm.com    BAR4Size = '16B'
4410259SAndrew.Bardsley@arm.com
4510259SAndrew.Bardsley@arm.comclass SinicPciData(PciConfigData):
4610259SAndrew.Bardsley@arm.com    VendorID = 0x1291
4710259SAndrew.Bardsley@arm.com    DeviceID = 0x1293
4810259SAndrew.Bardsley@arm.com    Status = 0x0290
4910259SAndrew.Bardsley@arm.com    SubClassCode = 0x00
5010259SAndrew.Bardsley@arm.com    ClassCode = 0x02
5110259SAndrew.Bardsley@arm.com    ProgIF = 0x00
5210259SAndrew.Bardsley@arm.com    BAR0 = 0x00000000
5310259SAndrew.Bardsley@arm.com    BAR1 = 0x00000000
5410259SAndrew.Bardsley@arm.com    BAR2 = 0x00000000
5510259SAndrew.Bardsley@arm.com    BAR3 = 0x00000000
5610259SAndrew.Bardsley@arm.com    BAR4 = 0x00000000
5710259SAndrew.Bardsley@arm.com    BAR5 = 0x00000000
5810259SAndrew.Bardsley@arm.com    MaximumLatency = 0x34
5910259SAndrew.Bardsley@arm.com    MinimumGrant = 0xb0
6010259SAndrew.Bardsley@arm.com    InterruptLine = 0x1e
6110259SAndrew.Bardsley@arm.com    InterruptPin = 0x01
6210259SAndrew.Bardsley@arm.com    BAR0Size = '64kB'
6310259SAndrew.Bardsley@arm.com
6410259SAndrew.Bardsley@arm.comclass NSGigEPciData(PciConfigData):
6510259SAndrew.Bardsley@arm.com    VendorID = 0x100B
6610259SAndrew.Bardsley@arm.com    DeviceID = 0x0022
6710259SAndrew.Bardsley@arm.com    Status = 0x0290
6810259SAndrew.Bardsley@arm.com    SubClassCode = 0x00
6910259SAndrew.Bardsley@arm.com    ClassCode = 0x02
7010259SAndrew.Bardsley@arm.com    ProgIF = 0x00
7110259SAndrew.Bardsley@arm.com    BAR0 = 0x00000001
7210259SAndrew.Bardsley@arm.com    BAR1 = 0x00000000
7310259SAndrew.Bardsley@arm.com    BAR2 = 0x00000000
7410259SAndrew.Bardsley@arm.com    BAR3 = 0x00000000
7510259SAndrew.Bardsley@arm.com    BAR4 = 0x00000000
7610259SAndrew.Bardsley@arm.com    BAR5 = 0x00000000
7710259SAndrew.Bardsley@arm.com    MaximumLatency = 0x34
7810259SAndrew.Bardsley@arm.com    MinimumGrant = 0xb0
7910259SAndrew.Bardsley@arm.com    InterruptLine = 0x1e
8010259SAndrew.Bardsley@arm.com    InterruptPin = 0x01
8110259SAndrew.Bardsley@arm.com    BAR0Size = '256B'
8210259SAndrew.Bardsley@arm.com    BAR1Size = '4kB'
8310259SAndrew.Bardsley@arm.com
8410259SAndrew.Bardsley@arm.comclass LinuxRootDisk(IdeDisk):
8510259SAndrew.Bardsley@arm.com    raw_image = RawDiskImage(image_file=linux_image, read_only=True)
8610259SAndrew.Bardsley@arm.com    image = CowDiskImage(child=Parent.raw_image, read_only=False)
8710259SAndrew.Bardsley@arm.com
8810259SAndrew.Bardsley@arm.comclass LinuxSwapDisk(IdeDisk):
8910259SAndrew.Bardsley@arm.com    raw_image = RawDiskImage(image_file = disk('linux-bigswap2.img'),
9010259SAndrew.Bardsley@arm.com                                  read_only=True)
9110259SAndrew.Bardsley@arm.com    image = CowDiskImage(child = Parent.raw_image, read_only=False)
9210259SAndrew.Bardsley@arm.com
9310259SAndrew.Bardsley@arm.comclass SpecwebFilesetDisk(IdeDisk):
9410259SAndrew.Bardsley@arm.com    raw_image = RawDiskImage(image_file = disk('specweb-fileset.img'),
9510259SAndrew.Bardsley@arm.com                                  read_only=True)
9610259SAndrew.Bardsley@arm.com    image = CowDiskImage(child = Parent.raw_image, read_only=False)
9710259SAndrew.Bardsley@arm.com
9810259SAndrew.Bardsley@arm.comclass BaseTsunami(Tsunami):
9910259SAndrew.Bardsley@arm.com    cchip = TsunamiCChip(pio_addr=0x801a0000000)
10010259SAndrew.Bardsley@arm.com    pchip = TsunamiPChip(pio_addr=0x80180000000)
10110259SAndrew.Bardsley@arm.com    pciconfig = PciConfigAll()
10210259SAndrew.Bardsley@arm.com    fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
10310259SAndrew.Bardsley@arm.com
10410259SAndrew.Bardsley@arm.com    fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
10510259SAndrew.Bardsley@arm.com    fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
10610259SAndrew.Bardsley@arm.com    fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
10710259SAndrew.Bardsley@arm.com    fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
10810259SAndrew.Bardsley@arm.com
10910259SAndrew.Bardsley@arm.com    fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
11010259SAndrew.Bardsley@arm.com
11110259SAndrew.Bardsley@arm.com    fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
11210259SAndrew.Bardsley@arm.com
11310259SAndrew.Bardsley@arm.com    fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
11410259SAndrew.Bardsley@arm.com    fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
11510259SAndrew.Bardsley@arm.com    fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
11610259SAndrew.Bardsley@arm.com    fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
11710259SAndrew.Bardsley@arm.com    fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
11810259SAndrew.Bardsley@arm.com    fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
11910259SAndrew.Bardsley@arm.com    fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
12010259SAndrew.Bardsley@arm.com    fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
12110259SAndrew.Bardsley@arm.com    fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
12210259SAndrew.Bardsley@arm.com    fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
12310259SAndrew.Bardsley@arm.com
12410259SAndrew.Bardsley@arm.com    fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
12510259SAndrew.Bardsley@arm.com    fake_ata1 = IsaFake(pio_addr=0x801fc000170)
12610259SAndrew.Bardsley@arm.com
12710259SAndrew.Bardsley@arm.com    fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
12810259SAndrew.Bardsley@arm.com    io = TsunamiIO(pio_addr=0x801fc000000)
12910259SAndrew.Bardsley@arm.com    uart = Uart8250(pio_addr=0x801fc0003f8)
13010259SAndrew.Bardsley@arm.com    ethernet = NSGigE(configdata=NSGigEPciData(),
13110259SAndrew.Bardsley@arm.com                      pci_bus=0, pci_dev=1, pci_func=0)
13210259SAndrew.Bardsley@arm.com    etherint = NSGigEInt(device=Parent.ethernet)
13310259SAndrew.Bardsley@arm.com    console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
13410259SAndrew.Bardsley@arm.com
13510259SAndrew.Bardsley@arm.comclass LinuxTsunami(BaseTsunami):
13610259SAndrew.Bardsley@arm.com    disk0 = LinuxRootDisk(driveID='master')
13710259SAndrew.Bardsley@arm.com    disk1 = SpecwebFilesetDisk(driveID='slave')
13810259SAndrew.Bardsley@arm.com    disk2 = LinuxSwapDisk(driveID='master')
13910259SAndrew.Bardsley@arm.com    ide = IdeController(disks=[Parent.disk0, Parent.disk1, Parent.disk2],
14010259SAndrew.Bardsley@arm.com                        configdata=IdeControllerPciData(),
14110259SAndrew.Bardsley@arm.com                        pci_func=0, pci_dev=0, pci_bus=0)
14210259SAndrew.Bardsley@arm.com
14310259SAndrew.Bardsley@arm.comclass MyLinuxAlphaSystem(LinuxAlphaSystem):
14410259SAndrew.Bardsley@arm.com    magicbus = Bus(bus_id=0)
14510259SAndrew.Bardsley@arm.com    magicbus2 = Bus(bus_id=1)
14610259SAndrew.Bardsley@arm.com    bridge = Bridge()
14710259SAndrew.Bardsley@arm.com    physmem = PhysicalMemory(range = AddrRange('128MB'))
14810259SAndrew.Bardsley@arm.com    bridge.side_a = magicbus.port
14910259SAndrew.Bardsley@arm.com    bridge.side_b = magicbus2.port
15010259SAndrew.Bardsley@arm.com    physmem.port = magicbus2.port
15110259SAndrew.Bardsley@arm.com    tsunami = LinuxTsunami()
15210259SAndrew.Bardsley@arm.com    tsunami.cchip.pio = magicbus.port
15310259SAndrew.Bardsley@arm.com    tsunami.pchip.pio = magicbus.port
15410259SAndrew.Bardsley@arm.com    tsunami.pciconfig.pio = magicbus.default
15510259SAndrew.Bardsley@arm.com    tsunami.fake_sm_chip.pio = magicbus.port
15610259SAndrew.Bardsley@arm.com    tsunami.ethernet.pio = magicbus.port
15710259SAndrew.Bardsley@arm.com    tsunami.ethernet.dma = magicbus.port
15810259SAndrew.Bardsley@arm.com    tsunami.ethernet.config = magicbus.port
15910259SAndrew.Bardsley@arm.com    tsunami.fake_uart1.pio = magicbus.port
16010259SAndrew.Bardsley@arm.com    tsunami.fake_uart2.pio = magicbus.port
16110259SAndrew.Bardsley@arm.com    tsunami.fake_uart3.pio = magicbus.port
16210259SAndrew.Bardsley@arm.com    tsunami.fake_uart4.pio = magicbus.port
16310259SAndrew.Bardsley@arm.com    tsunami.ide.pio = magicbus.port
16410259SAndrew.Bardsley@arm.com    tsunami.ide.dma = magicbus.port
16510259SAndrew.Bardsley@arm.com    tsunami.ide.config = magicbus.port
16610259SAndrew.Bardsley@arm.com    tsunami.fake_ppc.pio = magicbus.port
16710259SAndrew.Bardsley@arm.com    tsunami.fake_OROM.pio = magicbus.port
16810259SAndrew.Bardsley@arm.com    tsunami.fake_pnp_addr.pio = magicbus.port
16910259SAndrew.Bardsley@arm.com    tsunami.fake_pnp_write.pio = magicbus.port
17010259SAndrew.Bardsley@arm.com    tsunami.fake_pnp_read0.pio = magicbus.port
17110259SAndrew.Bardsley@arm.com    tsunami.fake_pnp_read1.pio = magicbus.port
17210259SAndrew.Bardsley@arm.com    tsunami.fake_pnp_read2.pio = magicbus.port
17310259SAndrew.Bardsley@arm.com    tsunami.fake_pnp_read3.pio = magicbus.port
17410259SAndrew.Bardsley@arm.com    tsunami.fake_pnp_read4.pio = magicbus.port
17510259SAndrew.Bardsley@arm.com    tsunami.fake_pnp_read5.pio = magicbus.port
17610259SAndrew.Bardsley@arm.com    tsunami.fake_pnp_read6.pio = magicbus.port
17710259SAndrew.Bardsley@arm.com    tsunami.fake_pnp_read7.pio = magicbus.port
17810259SAndrew.Bardsley@arm.com    tsunami.fake_ata0.pio = magicbus.port
17910259SAndrew.Bardsley@arm.com    tsunami.fake_ata1.pio = magicbus.port
18010259SAndrew.Bardsley@arm.com    tsunami.fb.pio = magicbus.port
18110259SAndrew.Bardsley@arm.com    tsunami.io.pio = magicbus.port
18210259SAndrew.Bardsley@arm.com    tsunami.uart.pio = magicbus.port
18310259SAndrew.Bardsley@arm.com    tsunami.console.pio = magicbus.port
18410259SAndrew.Bardsley@arm.com    raw_image = RawDiskImage(image_file=disk('linux-latest.img'),
18510259SAndrew.Bardsley@arm.com                             read_only=True)
18610259SAndrew.Bardsley@arm.com    simple_disk = SimpleDisk(disk=Parent.raw_image)
18710259SAndrew.Bardsley@arm.com    intrctrl = IntrControl()
18810259SAndrew.Bardsley@arm.com    if options.timing:
18910259SAndrew.Bardsley@arm.com        cpu = TimingSimpleCPU()
19010259SAndrew.Bardsley@arm.com    else:
19110259SAndrew.Bardsley@arm.com        cpu = AtomicSimpleCPU()
19210259SAndrew.Bardsley@arm.com    cpu.mem = magicbus2
19310259SAndrew.Bardsley@arm.com    cpu.icache_port = magicbus2.port
19410259SAndrew.Bardsley@arm.com    cpu.dcache_port = magicbus2.port
19510259SAndrew.Bardsley@arm.com    cpu.itb = AlphaITB()
19610259SAndrew.Bardsley@arm.com    cpu.dtb = AlphaDTB()
19710259SAndrew.Bardsley@arm.com    sim_console = SimConsole(listener=ConsoleListener(port=3456))
19810259SAndrew.Bardsley@arm.com    kernel = binary('vmlinux')
19910259SAndrew.Bardsley@arm.com    pal = binary('ts_osfpal')
20010259SAndrew.Bardsley@arm.com    console = binary('console')
20110259SAndrew.Bardsley@arm.com    boot_osflags = 'root=/dev/hda1 console=ttyS0'
20210259SAndrew.Bardsley@arm.com#    readfile = os.path.join(test_base, 'halt.sh')
20310259SAndrew.Bardsley@arm.com
20410259SAndrew.Bardsley@arm.com
20510259SAndrew.Bardsley@arm.com
20610259SAndrew.Bardsley@arm.comclass TsunamiRoot(System):
20710259SAndrew.Bardsley@arm.com    pass
20810259SAndrew.Bardsley@arm.com
20910259SAndrew.Bardsley@arm.com
21010259SAndrew.Bardsley@arm.comdef DualRoot(clientSystem, serverSystem):
21110259SAndrew.Bardsley@arm.com    self = Root()
21210259SAndrew.Bardsley@arm.com    self.client = clientSystem
21310259SAndrew.Bardsley@arm.com    self.server = serverSystem
21410259SAndrew.Bardsley@arm.com
21510259SAndrew.Bardsley@arm.com    self.etherdump = EtherDump(file='ethertrace')
21610259SAndrew.Bardsley@arm.com    self.etherlink = EtherLink(int1 = Parent.client.tsunami.etherint[0],
21710259SAndrew.Bardsley@arm.com                               int2 = Parent.server.tsunami.etherint[0],
21810259SAndrew.Bardsley@arm.com                               dump = Parent.etherdump)
21910259SAndrew.Bardsley@arm.com    self.clock = '5GHz'
22010259SAndrew.Bardsley@arm.com    return self
22110259SAndrew.Bardsley@arm.com
22210259SAndrew.Bardsley@arm.comroot = DualRoot(
22310259SAndrew.Bardsley@arm.com    MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
22410259SAndrew.Bardsley@arm.com    MyLinuxAlphaSystem(readfile=script('netperf-server.rcS')))
22510259SAndrew.Bardsley@arm.com
22610259SAndrew.Bardsley@arm.comm5.instantiate(root)
22710259SAndrew.Bardsley@arm.com
22810259SAndrew.Bardsley@arm.comexit_event = m5.simulate()
22910259SAndrew.Bardsley@arm.com
23010259SAndrew.Bardsley@arm.comprint 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause()
23110259SAndrew.Bardsley@arm.com