fs.py revision 11598
111598Sandreas.sandberg@arm.com# Copyright (c) 2010-2013, 2016 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 1310118Snilay@cs.wisc.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 1410118Snilay@cs.wisc.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 153970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 163005Sstever@eecs.umich.edu# All rights reserved. 173005Sstever@eecs.umich.edu# 183005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 193005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 203005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 223005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 233005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 243005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 253005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 263005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 273005Sstever@eecs.umich.edu# this software without specific prior written permission. 283005Sstever@eecs.umich.edu# 293005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403005Sstever@eecs.umich.edu# 413005Sstever@eecs.umich.edu# Authors: Ali Saidi 4210118Snilay@cs.wisc.edu# Brad Beckmann 433005Sstever@eecs.umich.edu 446654Snate@binkert.orgimport optparse 456654Snate@binkert.orgimport sys 462889SN/A 472710SN/Aimport m5 486654Snate@binkert.orgfrom m5.defines import buildEnv 496654Snate@binkert.orgfrom m5.objects import * 506654Snate@binkert.orgfrom m5.util import addToPath, fatal 515457Ssaidi@eecs.umich.edu 526654Snate@binkert.orgaddToPath('../common') 5310118Snilay@cs.wisc.eduaddToPath('../ruby') 5410118Snilay@cs.wisc.edu 5510118Snilay@cs.wisc.eduimport Ruby 566654Snate@binkert.org 572934SN/Afrom FSConfig import * 582549SN/Afrom SysPaths import * 592995SN/Afrom Benchmarks import * 603395Shsul@eecs.umich.eduimport Simulation 616981SLisa.Hsu@amd.comimport CacheConfig 629836Sandreas.hansson@arm.comimport MemConfig 633448Shsul@eecs.umich.edufrom Caches import * 648920Snilay@cs.wisc.eduimport Options 653444Sktlim@umich.edu 663304Sstever@eecs.umich.edu 679653SAndreas.Sandberg@ARM.com# Check if KVM support has been enabled, we might need to do VM 689653SAndreas.Sandberg@ARM.com# configuration if that's the case. 699653SAndreas.Sandberg@ARM.comhave_kvm_support = 'BaseKvmCPU' in globals() 709653SAndreas.Sandberg@ARM.comdef is_kvm_cpu(cpu_class): 719653SAndreas.Sandberg@ARM.com return have_kvm_support and cpu_class != None and \ 729653SAndreas.Sandberg@ARM.com issubclass(cpu_class, BaseKvmCPU) 739653SAndreas.Sandberg@ARM.com 7410594Sgabeblack@google.comdef cmd_line_template(): 7510594Sgabeblack@google.com if options.command_line and options.command_line_file: 7610594Sgabeblack@google.com print "Error: --command-line and --command-line-file are " \ 7710594Sgabeblack@google.com "mutually exclusive" 7810594Sgabeblack@google.com sys.exit(1) 7910594Sgabeblack@google.com if options.command_line: 8010594Sgabeblack@google.com return options.command_line 8110594Sgabeblack@google.com if options.command_line_file: 8210594Sgabeblack@google.com return open(options.command_line_file).read().strip() 8310594Sgabeblack@google.com return None 8410594Sgabeblack@google.com 8510119Snilay@cs.wisc.edudef build_test_system(np): 8610594Sgabeblack@google.com cmdline = cmd_line_template() 8710119Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "alpha": 8810594Sgabeblack@google.com test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 8910594Sgabeblack@google.com cmdline=cmdline) 9010119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "mips": 9110594Sgabeblack@google.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 9210119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "sparc": 9310594Sgabeblack@google.com test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 9410119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "x86": 9510119Snilay@cs.wisc.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 9610594Sgabeblack@google.com options.ruby, cmdline=cmdline) 9710119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "arm": 9810512SAli.Saidi@ARM.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, 9910512SAli.Saidi@ARM.com options.num_cpus, bm[0], options.dtb_filename, 10010594Sgabeblack@google.com bare_metal=options.bare_metal, 10110780SCurtis.Dunham@arm.com cmdline=cmdline, 10211598Sandreas.sandberg@arm.com external_memory=options.external_memory_system, 10311598Sandreas.sandberg@arm.com ruby=options.ruby) 10410119Snilay@cs.wisc.edu if options.enable_context_switch_stats_dump: 10510119Snilay@cs.wisc.edu test_sys.enable_context_switch_stats_dump = True 10610119Snilay@cs.wisc.edu else: 10710119Snilay@cs.wisc.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1082566SN/A 10910119Snilay@cs.wisc.edu # Set the cache line size for the entire system 11010119Snilay@cs.wisc.edu test_sys.cache_line_size = options.cacheline_size 1119665Sandreas.hansson@arm.com 11210119Snilay@cs.wisc.edu # Create a top-level voltage domain 11310119Snilay@cs.wisc.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 11410119Snilay@cs.wisc.edu 11510119Snilay@cs.wisc.edu # Create a source clock for the system and set the clock period 11610119Snilay@cs.wisc.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 11710119Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 11810119Snilay@cs.wisc.edu 11910119Snilay@cs.wisc.edu # Create a CPU voltage domain 12010119Snilay@cs.wisc.edu test_sys.cpu_voltage_domain = VoltageDomain() 12110119Snilay@cs.wisc.edu 12210119Snilay@cs.wisc.edu # Create a source clock for the CPUs and set the clock period 12310119Snilay@cs.wisc.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 12410119Snilay@cs.wisc.edu voltage_domain = 12510119Snilay@cs.wisc.edu test_sys.cpu_voltage_domain) 12610119Snilay@cs.wisc.edu 12710119Snilay@cs.wisc.edu if options.kernel is not None: 12810119Snilay@cs.wisc.edu test_sys.kernel = binary(options.kernel) 12910119Snilay@cs.wisc.edu 13010119Snilay@cs.wisc.edu if options.script is not None: 13110119Snilay@cs.wisc.edu test_sys.readfile = options.script 13210119Snilay@cs.wisc.edu 13310119Snilay@cs.wisc.edu if options.lpae: 13410119Snilay@cs.wisc.edu test_sys.have_lpae = True 13510119Snilay@cs.wisc.edu 13610119Snilay@cs.wisc.edu if options.virtualisation: 13710119Snilay@cs.wisc.edu test_sys.have_virtualization = True 13810119Snilay@cs.wisc.edu 13910119Snilay@cs.wisc.edu test_sys.init_param = options.init_param 14010119Snilay@cs.wisc.edu 14110119Snilay@cs.wisc.edu # For now, assign all the CPUs to the same clock domain 14210119Snilay@cs.wisc.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 14310119Snilay@cs.wisc.edu for i in xrange(np)] 14410119Snilay@cs.wisc.edu 14510119Snilay@cs.wisc.edu if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 14610119Snilay@cs.wisc.edu test_sys.vm = KvmVM() 14710119Snilay@cs.wisc.edu 14810119Snilay@cs.wisc.edu if options.ruby: 14910119Snilay@cs.wisc.edu # Check for timing mode because ruby does not support atomic accesses 15010119Snilay@cs.wisc.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 15110119Snilay@cs.wisc.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 15210119Snilay@cs.wisc.edu sys.exit(1) 15310119Snilay@cs.wisc.edu 15410519Snilay@cs.wisc.edu Ruby.create_system(options, True, test_sys, test_sys.iobus, 15510519Snilay@cs.wisc.edu test_sys._dma_ports) 15610119Snilay@cs.wisc.edu 15710119Snilay@cs.wisc.edu # Create a seperate clock domain for Ruby 15810119Snilay@cs.wisc.edu test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 15910119Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 16010119Snilay@cs.wisc.edu 16110547Snilay@cs.wisc.edu # Connect the ruby io port to the PIO bus, 16210547Snilay@cs.wisc.edu # assuming that there is just one such port. 16310547Snilay@cs.wisc.edu test_sys.iobus.master = test_sys.ruby._io_port.slave 16410547Snilay@cs.wisc.edu 16510119Snilay@cs.wisc.edu for (i, cpu) in enumerate(test_sys.cpu): 16610119Snilay@cs.wisc.edu # 16710119Snilay@cs.wisc.edu # Tie the cpu ports to the correct ruby system ports 16810119Snilay@cs.wisc.edu # 16910119Snilay@cs.wisc.edu cpu.clk_domain = test_sys.cpu_clk_domain 17010119Snilay@cs.wisc.edu cpu.createThreads() 17110119Snilay@cs.wisc.edu cpu.createInterruptController() 17210119Snilay@cs.wisc.edu 17310120Snilay@cs.wisc.edu cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 17410120Snilay@cs.wisc.edu cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 17510119Snilay@cs.wisc.edu 17611598Sandreas.sandberg@arm.com if buildEnv['TARGET_ISA'] in ("x86", "arm"): 17710120Snilay@cs.wisc.edu cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 17810120Snilay@cs.wisc.edu cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 17910119Snilay@cs.wisc.edu 18011598Sandreas.sandberg@arm.com if buildEnv['TARGET_ISA'] in "x86": 18111150Smitch.hayenga@arm.com cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 18211150Smitch.hayenga@arm.com cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 18311150Smitch.hayenga@arm.com cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 18410119Snilay@cs.wisc.edu 1852995SN/A else: 18610119Snilay@cs.wisc.edu if options.caches or options.l2cache: 18710119Snilay@cs.wisc.edu # By default the IOCache runs at the system clock 18810119Snilay@cs.wisc.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 18910119Snilay@cs.wisc.edu test_sys.iocache.cpu_side = test_sys.iobus.master 19010119Snilay@cs.wisc.edu test_sys.iocache.mem_side = test_sys.membus.slave 19110780SCurtis.Dunham@arm.com elif not options.external_memory_system: 19210119Snilay@cs.wisc.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 19310119Snilay@cs.wisc.edu test_sys.iobridge.slave = test_sys.iobus.master 19410119Snilay@cs.wisc.edu test_sys.iobridge.master = test_sys.membus.slave 1953304Sstever@eecs.umich.edu 19610119Snilay@cs.wisc.edu # Sanity check 19710119Snilay@cs.wisc.edu if options.fastmem: 19810119Snilay@cs.wisc.edu if TestCPUClass != AtomicSimpleCPU: 19910119Snilay@cs.wisc.edu fatal("Fastmem can only be used with atomic CPU!") 20010119Snilay@cs.wisc.edu if (options.caches or options.l2cache): 20110119Snilay@cs.wisc.edu fatal("You cannot use fastmem in combination with caches!") 2026135Sgblack@eecs.umich.edu 20310608Sdam.sunwoo@arm.com if options.simpoint_profile: 20410608Sdam.sunwoo@arm.com if not options.fastmem: 20510608Sdam.sunwoo@arm.com # Atomic CPU checked with fastmem option already 20610608Sdam.sunwoo@arm.com fatal("SimPoint generation should be done with atomic cpu and fastmem") 20710608Sdam.sunwoo@arm.com if np > 1: 20810608Sdam.sunwoo@arm.com fatal("SimPoint generation not supported with more than one CPUs") 20910608Sdam.sunwoo@arm.com 21010119Snilay@cs.wisc.edu for i in xrange(np): 21110119Snilay@cs.wisc.edu if options.fastmem: 21210119Snilay@cs.wisc.edu test_sys.cpu[i].fastmem = True 21310608Sdam.sunwoo@arm.com if options.simpoint_profile: 21410608Sdam.sunwoo@arm.com test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 21510119Snilay@cs.wisc.edu if options.checker: 21610119Snilay@cs.wisc.edu test_sys.cpu[i].addCheckerCpu() 21710119Snilay@cs.wisc.edu test_sys.cpu[i].createThreads() 2183819Shsul@eecs.umich.edu 21911251Sradhika.jagtap@ARM.com # If elastic tracing is enabled when not restoring from checkpoint and 22011251Sradhika.jagtap@ARM.com # when not fast forwarding using the atomic cpu, then check that the 22111251Sradhika.jagtap@ARM.com # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 22211251Sradhika.jagtap@ARM.com # passes then attach the elastic trace probe. 22311251Sradhika.jagtap@ARM.com # If restoring from checkpoint or fast forwarding, the code that does this for 22411251Sradhika.jagtap@ARM.com # FutureCPUClass is in the Simulation module. If the check passes then the 22511251Sradhika.jagtap@ARM.com # elastic trace probe is attached to the switch CPUs. 22611251Sradhika.jagtap@ARM.com if options.elastic_trace_en and options.checkpoint_restore == None and \ 22711251Sradhika.jagtap@ARM.com not options.fast_forward: 22811251Sradhika.jagtap@ARM.com CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 22911251Sradhika.jagtap@ARM.com 23010119Snilay@cs.wisc.edu CacheConfig.config_cache(options, test_sys) 23111183Serfan.azarkhish@unibo.it 23210119Snilay@cs.wisc.edu MemConfig.config_mem(options, test_sys) 23310118Snilay@cs.wisc.edu 23410119Snilay@cs.wisc.edu return test_sys 2359827Sakash.bagdia@arm.com 23610119Snilay@cs.wisc.edudef build_drive_system(np): 23710119Snilay@cs.wisc.edu # driver system CPU is always simple, so is the memory 23810119Snilay@cs.wisc.edu # Note this is an assignment of a class, not an instance. 23910119Snilay@cs.wisc.edu DriveCPUClass = AtomicSimpleCPU 24010119Snilay@cs.wisc.edu drive_mem_mode = 'atomic' 24110119Snilay@cs.wisc.edu DriveMemClass = SimpleMemory 2429827Sakash.bagdia@arm.com 24310594Sgabeblack@google.com cmdline = cmd_line_template() 2446654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'alpha': 24510594Sgabeblack@google.com drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2466654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 24710594Sgabeblack@google.com drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2486654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'sparc': 24910594Sgabeblack@google.com drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2506654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 25110594Sgabeblack@google.com drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 25210594Sgabeblack@google.com cmdline=cmdline) 2537586SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 25410635Satgutier@umich.edu drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 25510635Satgutier@umich.edu bm[1], options.dtb_filename, cmdline=cmdline) 2568661SAli.Saidi@ARM.com 2579827Sakash.bagdia@arm.com # Create a top-level voltage domain 2589827Sakash.bagdia@arm.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 2599827Sakash.bagdia@arm.com 2609793Sakash.bagdia@arm.com # Create a source clock for the system and set the clock period 26110119Snilay@cs.wisc.edu drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 26210119Snilay@cs.wisc.edu voltage_domain = drive_sys.voltage_domain) 2639790Sakash.bagdia@arm.com 2649827Sakash.bagdia@arm.com # Create a CPU voltage domain 2659827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain = VoltageDomain() 2669827Sakash.bagdia@arm.com 2679793Sakash.bagdia@arm.com # Create a source clock for the CPUs and set the clock period 2689827Sakash.bagdia@arm.com drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2699827Sakash.bagdia@arm.com voltage_domain = 2709827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain) 2719793Sakash.bagdia@arm.com 2729793Sakash.bagdia@arm.com drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2739793Sakash.bagdia@arm.com cpu_id=0) 2749384SAndreas.Sandberg@arm.com drive_sys.cpu.createThreads() 2758863Snilay@cs.wisc.edu drive_sys.cpu.createInterruptController() 2767876Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2774968Sacolyte@umich.edu if options.fastmem: 2788926Sandreas.hansson@arm.com drive_sys.cpu.fastmem = True 2794837Ssaidi@eecs.umich.edu if options.kernel is not None: 2804837Ssaidi@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2819408Sandreas.hansson@arm.com 2829653SAndreas.Sandberg@ARM.com if is_kvm_cpu(DriveCPUClass): 2839653SAndreas.Sandberg@ARM.com drive_sys.vm = KvmVM() 2849653SAndreas.Sandberg@ARM.com 2859164Sandreas.hansson@arm.com drive_sys.iobridge = Bridge(delay='50ns', 2869408Sandreas.hansson@arm.com ranges = drive_sys.mem_ranges) 2878845Sandreas.hansson@arm.com drive_sys.iobridge.slave = drive_sys.iobus.master 2888845Sandreas.hansson@arm.com drive_sys.iobridge.master = drive_sys.membus.slave 2894837Ssaidi@eecs.umich.edu 2909826Sandreas.hansson@arm.com # Create the appropriate memory controllers and connect them to the 2919826Sandreas.hansson@arm.com # memory bus 2929835Sandreas.hansson@arm.com drive_sys.mem_ctrls = [DriveMemClass(range = r) 2939826Sandreas.hansson@arm.com for r in drive_sys.mem_ranges] 2949826Sandreas.hansson@arm.com for i in xrange(len(drive_sys.mem_ctrls)): 2959826Sandreas.hansson@arm.com drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2969826Sandreas.hansson@arm.com 2978659SAli.Saidi@ARM.com drive_sys.init_param = options.init_param 29810119Snilay@cs.wisc.edu 29910119Snilay@cs.wisc.edu return drive_sys 30010119Snilay@cs.wisc.edu 30110119Snilay@cs.wisc.edu# Add options 30210119Snilay@cs.wisc.eduparser = optparse.OptionParser() 30310119Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 30410119Snilay@cs.wisc.eduOptions.addFSOptions(parser) 30510119Snilay@cs.wisc.edu 30610119Snilay@cs.wisc.edu# Add the ruby specific and protocol specific options 30710119Snilay@cs.wisc.eduif '--ruby' in sys.argv: 30810119Snilay@cs.wisc.edu Ruby.define_options(parser) 30910119Snilay@cs.wisc.edu 31010119Snilay@cs.wisc.edu(options, args) = parser.parse_args() 31110119Snilay@cs.wisc.edu 31210119Snilay@cs.wisc.eduif args: 31310119Snilay@cs.wisc.edu print "Error: script doesn't take any positional arguments" 31410119Snilay@cs.wisc.edu sys.exit(1) 31510119Snilay@cs.wisc.edu 31610119Snilay@cs.wisc.edu# system under test can be any CPU 31710119Snilay@cs.wisc.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 31810119Snilay@cs.wisc.edu 31910119Snilay@cs.wisc.edu# Match the memories with the CPUs, based on the options for the test system 32010119Snilay@cs.wisc.eduTestMemClass = Simulation.setMemClass(options) 32110119Snilay@cs.wisc.edu 32210119Snilay@cs.wisc.eduif options.benchmark: 32310119Snilay@cs.wisc.edu try: 32410119Snilay@cs.wisc.edu bm = Benchmarks[options.benchmark] 32510119Snilay@cs.wisc.edu except KeyError: 32610119Snilay@cs.wisc.edu print "Error benchmark %s has not been defined." % options.benchmark 32710119Snilay@cs.wisc.edu print "Valid benchmarks are: %s" % DefinedBenchmarks 32810119Snilay@cs.wisc.edu sys.exit(1) 32910119Snilay@cs.wisc.eduelse: 33010119Snilay@cs.wisc.edu if options.dual: 33110697SCurtis.Dunham@arm.com bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 33210747SChris.Emmons@arm.com mem=options.mem_size, os_type=options.os_type), 33310697SCurtis.Dunham@arm.com SysConfig(disk=options.disk_image, rootdev=options.root_device, 33410747SChris.Emmons@arm.com mem=options.mem_size, os_type=options.os_type)] 33510119Snilay@cs.wisc.edu else: 33610697SCurtis.Dunham@arm.com bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 33710747SChris.Emmons@arm.com mem=options.mem_size, os_type=options.os_type)] 33810119Snilay@cs.wisc.edu 33910119Snilay@cs.wisc.edunp = options.num_cpus 34010119Snilay@cs.wisc.edu 34110119Snilay@cs.wisc.edutest_sys = build_test_system(np) 34210119Snilay@cs.wisc.eduif len(bm) == 2: 34310119Snilay@cs.wisc.edu drive_sys = build_drive_system(np) 3448801Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 34511291Sgabor.dozsa@arm.comelif len(bm) == 1 and options.dist: 34611291Sgabor.dozsa@arm.com # This system is part of a dist-gem5 simulation 34711291Sgabor.dozsa@arm.com root = makeDistRoot(test_sys, 34811291Sgabor.dozsa@arm.com options.dist_rank, 34911291Sgabor.dozsa@arm.com options.dist_size, 35011291Sgabor.dozsa@arm.com options.dist_server_name, 35111291Sgabor.dozsa@arm.com options.dist_server_port, 35211291Sgabor.dozsa@arm.com options.dist_sync_repeat, 35311291Sgabor.dozsa@arm.com options.dist_sync_start, 35411291Sgabor.dozsa@arm.com options.ethernet_linkspeed, 35511291Sgabor.dozsa@arm.com options.ethernet_linkdelay, 35611291Sgabor.dozsa@arm.com options.etherdump); 3573005Sstever@eecs.umich.eduelif len(bm) == 1: 3588801Sgblack@eecs.umich.edu root = Root(full_system=True, system=test_sys) 3593005Sstever@eecs.umich.eduelse: 3603005Sstever@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 3613005Sstever@eecs.umich.edu sys.exit(1) 3622566SN/A 3637861Sgblack@eecs.umich.eduif options.timesync: 3647861Sgblack@eecs.umich.edu root.time_sync_enable = True 3657861Sgblack@eecs.umich.edu 3668635Schris.emmons@arm.comif options.frame_capture: 3678635Schris.emmons@arm.com VncServer.frame_capture = True 3688635Schris.emmons@arm.com 3699061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options) 3703481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 371