fs.py revision 10635
19793Sakash.bagdia@arm.com# Copyright (c) 2010-2013 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 1310118Snilay@cs.wisc.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 1410118Snilay@cs.wisc.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 153970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 163005Sstever@eecs.umich.edu# All rights reserved. 173005Sstever@eecs.umich.edu# 183005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 193005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 203005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 223005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 233005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 243005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 253005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 263005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 273005Sstever@eecs.umich.edu# this software without specific prior written permission. 283005Sstever@eecs.umich.edu# 293005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403005Sstever@eecs.umich.edu# 413005Sstever@eecs.umich.edu# Authors: Ali Saidi 4210118Snilay@cs.wisc.edu# Brad Beckmann 433005Sstever@eecs.umich.edu 446654Snate@binkert.orgimport optparse 456654Snate@binkert.orgimport sys 462889SN/A 472710SN/Aimport m5 486654Snate@binkert.orgfrom m5.defines import buildEnv 496654Snate@binkert.orgfrom m5.objects import * 506654Snate@binkert.orgfrom m5.util import addToPath, fatal 515457Ssaidi@eecs.umich.edu 526654Snate@binkert.orgaddToPath('../common') 5310118Snilay@cs.wisc.eduaddToPath('../ruby') 5410118Snilay@cs.wisc.edu 5510118Snilay@cs.wisc.eduimport Ruby 566654Snate@binkert.org 572934SN/Afrom FSConfig import * 582549SN/Afrom SysPaths import * 592995SN/Afrom Benchmarks import * 603395Shsul@eecs.umich.eduimport Simulation 616981SLisa.Hsu@amd.comimport CacheConfig 629836Sandreas.hansson@arm.comimport MemConfig 633448Shsul@eecs.umich.edufrom Caches import * 648920Snilay@cs.wisc.eduimport Options 653444Sktlim@umich.edu 663304Sstever@eecs.umich.edu 679653SAndreas.Sandberg@ARM.com# Check if KVM support has been enabled, we might need to do VM 689653SAndreas.Sandberg@ARM.com# configuration if that's the case. 699653SAndreas.Sandberg@ARM.comhave_kvm_support = 'BaseKvmCPU' in globals() 709653SAndreas.Sandberg@ARM.comdef is_kvm_cpu(cpu_class): 719653SAndreas.Sandberg@ARM.com return have_kvm_support and cpu_class != None and \ 729653SAndreas.Sandberg@ARM.com issubclass(cpu_class, BaseKvmCPU) 739653SAndreas.Sandberg@ARM.com 7410594Sgabeblack@google.comdef cmd_line_template(): 7510594Sgabeblack@google.com if options.command_line and options.command_line_file: 7610594Sgabeblack@google.com print "Error: --command-line and --command-line-file are " \ 7710594Sgabeblack@google.com "mutually exclusive" 7810594Sgabeblack@google.com sys.exit(1) 7910594Sgabeblack@google.com if options.command_line: 8010594Sgabeblack@google.com return options.command_line 8110594Sgabeblack@google.com if options.command_line_file: 8210594Sgabeblack@google.com return open(options.command_line_file).read().strip() 8310594Sgabeblack@google.com return None 8410594Sgabeblack@google.com 8510119Snilay@cs.wisc.edudef build_test_system(np): 8610594Sgabeblack@google.com cmdline = cmd_line_template() 8710119Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "alpha": 8810594Sgabeblack@google.com test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 8910594Sgabeblack@google.com cmdline=cmdline) 9010119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "mips": 9110594Sgabeblack@google.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 9210119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "sparc": 9310594Sgabeblack@google.com test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 9410119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "x86": 9510119Snilay@cs.wisc.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 9610594Sgabeblack@google.com options.ruby, cmdline=cmdline) 9710119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "arm": 9810512SAli.Saidi@ARM.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, 9910512SAli.Saidi@ARM.com options.num_cpus, bm[0], options.dtb_filename, 10010594Sgabeblack@google.com bare_metal=options.bare_metal, 10110594Sgabeblack@google.com cmdline=cmdline) 10210119Snilay@cs.wisc.edu if options.enable_context_switch_stats_dump: 10310119Snilay@cs.wisc.edu test_sys.enable_context_switch_stats_dump = True 10410119Snilay@cs.wisc.edu else: 10510119Snilay@cs.wisc.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1062566SN/A 10710119Snilay@cs.wisc.edu # Set the cache line size for the entire system 10810119Snilay@cs.wisc.edu test_sys.cache_line_size = options.cacheline_size 1099665Sandreas.hansson@arm.com 11010119Snilay@cs.wisc.edu # Create a top-level voltage domain 11110119Snilay@cs.wisc.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 11210119Snilay@cs.wisc.edu 11310119Snilay@cs.wisc.edu # Create a source clock for the system and set the clock period 11410119Snilay@cs.wisc.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 11510119Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 11610119Snilay@cs.wisc.edu 11710119Snilay@cs.wisc.edu # Create a CPU voltage domain 11810119Snilay@cs.wisc.edu test_sys.cpu_voltage_domain = VoltageDomain() 11910119Snilay@cs.wisc.edu 12010119Snilay@cs.wisc.edu # Create a source clock for the CPUs and set the clock period 12110119Snilay@cs.wisc.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 12210119Snilay@cs.wisc.edu voltage_domain = 12310119Snilay@cs.wisc.edu test_sys.cpu_voltage_domain) 12410119Snilay@cs.wisc.edu 12510119Snilay@cs.wisc.edu if options.kernel is not None: 12610119Snilay@cs.wisc.edu test_sys.kernel = binary(options.kernel) 12710119Snilay@cs.wisc.edu 12810119Snilay@cs.wisc.edu if options.script is not None: 12910119Snilay@cs.wisc.edu test_sys.readfile = options.script 13010119Snilay@cs.wisc.edu 13110119Snilay@cs.wisc.edu if options.lpae: 13210119Snilay@cs.wisc.edu test_sys.have_lpae = True 13310119Snilay@cs.wisc.edu 13410119Snilay@cs.wisc.edu if options.virtualisation: 13510119Snilay@cs.wisc.edu test_sys.have_virtualization = True 13610119Snilay@cs.wisc.edu 13710119Snilay@cs.wisc.edu test_sys.init_param = options.init_param 13810119Snilay@cs.wisc.edu 13910119Snilay@cs.wisc.edu # For now, assign all the CPUs to the same clock domain 14010119Snilay@cs.wisc.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 14110119Snilay@cs.wisc.edu for i in xrange(np)] 14210119Snilay@cs.wisc.edu 14310119Snilay@cs.wisc.edu if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 14410119Snilay@cs.wisc.edu test_sys.vm = KvmVM() 14510119Snilay@cs.wisc.edu 14610119Snilay@cs.wisc.edu if options.ruby: 14710119Snilay@cs.wisc.edu # Check for timing mode because ruby does not support atomic accesses 14810119Snilay@cs.wisc.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 14910119Snilay@cs.wisc.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 15010119Snilay@cs.wisc.edu sys.exit(1) 15110119Snilay@cs.wisc.edu 15210519Snilay@cs.wisc.edu Ruby.create_system(options, True, test_sys, test_sys.iobus, 15310519Snilay@cs.wisc.edu test_sys._dma_ports) 15410119Snilay@cs.wisc.edu 15510119Snilay@cs.wisc.edu # Create a seperate clock domain for Ruby 15610119Snilay@cs.wisc.edu test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 15710119Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 15810119Snilay@cs.wisc.edu 15910547Snilay@cs.wisc.edu # Connect the ruby io port to the PIO bus, 16010547Snilay@cs.wisc.edu # assuming that there is just one such port. 16110547Snilay@cs.wisc.edu test_sys.iobus.master = test_sys.ruby._io_port.slave 16210547Snilay@cs.wisc.edu 16310119Snilay@cs.wisc.edu for (i, cpu) in enumerate(test_sys.cpu): 16410119Snilay@cs.wisc.edu # 16510119Snilay@cs.wisc.edu # Tie the cpu ports to the correct ruby system ports 16610119Snilay@cs.wisc.edu # 16710119Snilay@cs.wisc.edu cpu.clk_domain = test_sys.cpu_clk_domain 16810119Snilay@cs.wisc.edu cpu.createThreads() 16910119Snilay@cs.wisc.edu cpu.createInterruptController() 17010119Snilay@cs.wisc.edu 17110120Snilay@cs.wisc.edu cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 17210120Snilay@cs.wisc.edu cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 17310119Snilay@cs.wisc.edu 17410119Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "x86": 17510120Snilay@cs.wisc.edu cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 17610120Snilay@cs.wisc.edu cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 17710119Snilay@cs.wisc.edu 17810120Snilay@cs.wisc.edu cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master 17910120Snilay@cs.wisc.edu cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave 18010120Snilay@cs.wisc.edu cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master 18110119Snilay@cs.wisc.edu 1822995SN/A else: 18310119Snilay@cs.wisc.edu if options.caches or options.l2cache: 18410119Snilay@cs.wisc.edu # By default the IOCache runs at the system clock 18510119Snilay@cs.wisc.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 18610119Snilay@cs.wisc.edu test_sys.iocache.cpu_side = test_sys.iobus.master 18710119Snilay@cs.wisc.edu test_sys.iocache.mem_side = test_sys.membus.slave 18810119Snilay@cs.wisc.edu else: 18910119Snilay@cs.wisc.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 19010119Snilay@cs.wisc.edu test_sys.iobridge.slave = test_sys.iobus.master 19110119Snilay@cs.wisc.edu test_sys.iobridge.master = test_sys.membus.slave 1923304Sstever@eecs.umich.edu 19310119Snilay@cs.wisc.edu # Sanity check 19410119Snilay@cs.wisc.edu if options.fastmem: 19510119Snilay@cs.wisc.edu if TestCPUClass != AtomicSimpleCPU: 19610119Snilay@cs.wisc.edu fatal("Fastmem can only be used with atomic CPU!") 19710119Snilay@cs.wisc.edu if (options.caches or options.l2cache): 19810119Snilay@cs.wisc.edu fatal("You cannot use fastmem in combination with caches!") 1996135Sgblack@eecs.umich.edu 20010608Sdam.sunwoo@arm.com if options.simpoint_profile: 20110608Sdam.sunwoo@arm.com if not options.fastmem: 20210608Sdam.sunwoo@arm.com # Atomic CPU checked with fastmem option already 20310608Sdam.sunwoo@arm.com fatal("SimPoint generation should be done with atomic cpu and fastmem") 20410608Sdam.sunwoo@arm.com if np > 1: 20510608Sdam.sunwoo@arm.com fatal("SimPoint generation not supported with more than one CPUs") 20610608Sdam.sunwoo@arm.com 20710119Snilay@cs.wisc.edu for i in xrange(np): 20810119Snilay@cs.wisc.edu if options.fastmem: 20910119Snilay@cs.wisc.edu test_sys.cpu[i].fastmem = True 21010608Sdam.sunwoo@arm.com if options.simpoint_profile: 21110608Sdam.sunwoo@arm.com test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 21210119Snilay@cs.wisc.edu if options.checker: 21310119Snilay@cs.wisc.edu test_sys.cpu[i].addCheckerCpu() 21410119Snilay@cs.wisc.edu test_sys.cpu[i].createThreads() 2153819Shsul@eecs.umich.edu 21610119Snilay@cs.wisc.edu CacheConfig.config_cache(options, test_sys) 21710119Snilay@cs.wisc.edu MemConfig.config_mem(options, test_sys) 21810118Snilay@cs.wisc.edu 21910119Snilay@cs.wisc.edu return test_sys 2209827Sakash.bagdia@arm.com 22110119Snilay@cs.wisc.edudef build_drive_system(np): 22210119Snilay@cs.wisc.edu # driver system CPU is always simple, so is the memory 22310119Snilay@cs.wisc.edu # Note this is an assignment of a class, not an instance. 22410119Snilay@cs.wisc.edu DriveCPUClass = AtomicSimpleCPU 22510119Snilay@cs.wisc.edu drive_mem_mode = 'atomic' 22610119Snilay@cs.wisc.edu DriveMemClass = SimpleMemory 2279827Sakash.bagdia@arm.com 22810594Sgabeblack@google.com cmdline = cmd_line_template() 2296654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'alpha': 23010594Sgabeblack@google.com drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2316654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 23210594Sgabeblack@google.com drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2336654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'sparc': 23410594Sgabeblack@google.com drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 2356654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 23610594Sgabeblack@google.com drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 23710594Sgabeblack@google.com cmdline=cmdline) 2387586SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 23910635Satgutier@umich.edu drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 24010635Satgutier@umich.edu bm[1], options.dtb_filename, cmdline=cmdline) 2418661SAli.Saidi@ARM.com 2429827Sakash.bagdia@arm.com # Create a top-level voltage domain 2439827Sakash.bagdia@arm.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 2449827Sakash.bagdia@arm.com 2459793Sakash.bagdia@arm.com # Create a source clock for the system and set the clock period 24610119Snilay@cs.wisc.edu drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 24710119Snilay@cs.wisc.edu voltage_domain = drive_sys.voltage_domain) 2489790Sakash.bagdia@arm.com 2499827Sakash.bagdia@arm.com # Create a CPU voltage domain 2509827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain = VoltageDomain() 2519827Sakash.bagdia@arm.com 2529793Sakash.bagdia@arm.com # Create a source clock for the CPUs and set the clock period 2539827Sakash.bagdia@arm.com drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2549827Sakash.bagdia@arm.com voltage_domain = 2559827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain) 2569793Sakash.bagdia@arm.com 2579793Sakash.bagdia@arm.com drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2589793Sakash.bagdia@arm.com cpu_id=0) 2599384SAndreas.Sandberg@arm.com drive_sys.cpu.createThreads() 2608863Snilay@cs.wisc.edu drive_sys.cpu.createInterruptController() 2617876Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2624968Sacolyte@umich.edu if options.fastmem: 2638926Sandreas.hansson@arm.com drive_sys.cpu.fastmem = True 2644837Ssaidi@eecs.umich.edu if options.kernel is not None: 2654837Ssaidi@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2669408Sandreas.hansson@arm.com 2679653SAndreas.Sandberg@ARM.com if is_kvm_cpu(DriveCPUClass): 2689653SAndreas.Sandberg@ARM.com drive_sys.vm = KvmVM() 2699653SAndreas.Sandberg@ARM.com 2709164Sandreas.hansson@arm.com drive_sys.iobridge = Bridge(delay='50ns', 2719408Sandreas.hansson@arm.com ranges = drive_sys.mem_ranges) 2728845Sandreas.hansson@arm.com drive_sys.iobridge.slave = drive_sys.iobus.master 2738845Sandreas.hansson@arm.com drive_sys.iobridge.master = drive_sys.membus.slave 2744837Ssaidi@eecs.umich.edu 2759826Sandreas.hansson@arm.com # Create the appropriate memory controllers and connect them to the 2769826Sandreas.hansson@arm.com # memory bus 2779835Sandreas.hansson@arm.com drive_sys.mem_ctrls = [DriveMemClass(range = r) 2789826Sandreas.hansson@arm.com for r in drive_sys.mem_ranges] 2799826Sandreas.hansson@arm.com for i in xrange(len(drive_sys.mem_ctrls)): 2809826Sandreas.hansson@arm.com drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2819826Sandreas.hansson@arm.com 2828659SAli.Saidi@ARM.com drive_sys.init_param = options.init_param 28310119Snilay@cs.wisc.edu 28410119Snilay@cs.wisc.edu return drive_sys 28510119Snilay@cs.wisc.edu 28610119Snilay@cs.wisc.edu# Add options 28710119Snilay@cs.wisc.eduparser = optparse.OptionParser() 28810119Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 28910119Snilay@cs.wisc.eduOptions.addFSOptions(parser) 29010119Snilay@cs.wisc.edu 29110119Snilay@cs.wisc.edu# Add the ruby specific and protocol specific options 29210119Snilay@cs.wisc.eduif '--ruby' in sys.argv: 29310119Snilay@cs.wisc.edu Ruby.define_options(parser) 29410119Snilay@cs.wisc.edu 29510119Snilay@cs.wisc.edu(options, args) = parser.parse_args() 29610119Snilay@cs.wisc.edu 29710119Snilay@cs.wisc.eduif args: 29810119Snilay@cs.wisc.edu print "Error: script doesn't take any positional arguments" 29910119Snilay@cs.wisc.edu sys.exit(1) 30010119Snilay@cs.wisc.edu 30110119Snilay@cs.wisc.edu# system under test can be any CPU 30210119Snilay@cs.wisc.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 30310119Snilay@cs.wisc.edu 30410119Snilay@cs.wisc.edu# Match the memories with the CPUs, based on the options for the test system 30510119Snilay@cs.wisc.eduTestMemClass = Simulation.setMemClass(options) 30610119Snilay@cs.wisc.edu 30710119Snilay@cs.wisc.eduif options.benchmark: 30810119Snilay@cs.wisc.edu try: 30910119Snilay@cs.wisc.edu bm = Benchmarks[options.benchmark] 31010119Snilay@cs.wisc.edu except KeyError: 31110119Snilay@cs.wisc.edu print "Error benchmark %s has not been defined." % options.benchmark 31210119Snilay@cs.wisc.edu print "Valid benchmarks are: %s" % DefinedBenchmarks 31310119Snilay@cs.wisc.edu sys.exit(1) 31410119Snilay@cs.wisc.eduelse: 31510119Snilay@cs.wisc.edu if options.dual: 31610119Snilay@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), 31710119Snilay@cs.wisc.edu SysConfig(disk=options.disk_image, mem=options.mem_size)] 31810119Snilay@cs.wisc.edu else: 31910119Snilay@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 32010119Snilay@cs.wisc.edu 32110119Snilay@cs.wisc.edunp = options.num_cpus 32210119Snilay@cs.wisc.edu 32310119Snilay@cs.wisc.edutest_sys = build_test_system(np) 32410119Snilay@cs.wisc.eduif len(bm) == 2: 32510119Snilay@cs.wisc.edu drive_sys = build_drive_system(np) 3268801Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 3273005Sstever@eecs.umich.eduelif len(bm) == 1: 3288801Sgblack@eecs.umich.edu root = Root(full_system=True, system=test_sys) 3293005Sstever@eecs.umich.eduelse: 3303005Sstever@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 3313005Sstever@eecs.umich.edu sys.exit(1) 3322566SN/A 3337861Sgblack@eecs.umich.eduif options.timesync: 3347861Sgblack@eecs.umich.edu root.time_sync_enable = True 3357861Sgblack@eecs.umich.edu 3368635Schris.emmons@arm.comif options.frame_capture: 3378635Schris.emmons@arm.com VncServer.frame_capture = True 3388635Schris.emmons@arm.com 3399061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options) 3403481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 341