fs.py revision 10119
19793Sakash.bagdia@arm.com# Copyright (c) 2010-2013 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 1310118Snilay@cs.wisc.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 1410118Snilay@cs.wisc.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 153970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 163005Sstever@eecs.umich.edu# All rights reserved. 173005Sstever@eecs.umich.edu# 183005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 193005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 203005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 223005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 233005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 243005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 253005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 263005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 273005Sstever@eecs.umich.edu# this software without specific prior written permission. 283005Sstever@eecs.umich.edu# 293005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403005Sstever@eecs.umich.edu# 413005Sstever@eecs.umich.edu# Authors: Ali Saidi 4210118Snilay@cs.wisc.edu# Brad Beckmann 433005Sstever@eecs.umich.edu 446654Snate@binkert.orgimport optparse 456654Snate@binkert.orgimport sys 462889SN/A 472710SN/Aimport m5 486654Snate@binkert.orgfrom m5.defines import buildEnv 496654Snate@binkert.orgfrom m5.objects import * 506654Snate@binkert.orgfrom m5.util import addToPath, fatal 515457Ssaidi@eecs.umich.edu 526654Snate@binkert.orgaddToPath('../common') 5310118Snilay@cs.wisc.eduaddToPath('../ruby') 5410118Snilay@cs.wisc.edu 5510118Snilay@cs.wisc.eduimport Ruby 566654Snate@binkert.org 572934SN/Afrom FSConfig import * 582549SN/Afrom SysPaths import * 592995SN/Afrom Benchmarks import * 603395Shsul@eecs.umich.eduimport Simulation 616981SLisa.Hsu@amd.comimport CacheConfig 629836Sandreas.hansson@arm.comimport MemConfig 633448Shsul@eecs.umich.edufrom Caches import * 648920Snilay@cs.wisc.eduimport Options 653444Sktlim@umich.edu 663304Sstever@eecs.umich.edu 679653SAndreas.Sandberg@ARM.com# Check if KVM support has been enabled, we might need to do VM 689653SAndreas.Sandberg@ARM.com# configuration if that's the case. 699653SAndreas.Sandberg@ARM.comhave_kvm_support = 'BaseKvmCPU' in globals() 709653SAndreas.Sandberg@ARM.comdef is_kvm_cpu(cpu_class): 719653SAndreas.Sandberg@ARM.com return have_kvm_support and cpu_class != None and \ 729653SAndreas.Sandberg@ARM.com issubclass(cpu_class, BaseKvmCPU) 739653SAndreas.Sandberg@ARM.com 7410119Snilay@cs.wisc.edudef build_test_system(np): 7510119Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "alpha": 7610119Snilay@cs.wisc.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby) 7710119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "mips": 7810119Snilay@cs.wisc.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 7910119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "sparc": 8010119Snilay@cs.wisc.edu test_sys = makeSparcSystem(test_mem_mode, bm[0]) 8110119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "x86": 8210119Snilay@cs.wisc.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 8310119Snilay@cs.wisc.edu options.ruby) 8410119Snilay@cs.wisc.edu elif buildEnv['TARGET_ISA'] == "arm": 8510119Snilay@cs.wisc.edu test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 8610119Snilay@cs.wisc.edu options.dtb_filename, 8710119Snilay@cs.wisc.edu bare_metal=options.bare_metal) 8810119Snilay@cs.wisc.edu if options.enable_context_switch_stats_dump: 8910119Snilay@cs.wisc.edu test_sys.enable_context_switch_stats_dump = True 9010119Snilay@cs.wisc.edu else: 9110119Snilay@cs.wisc.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 922566SN/A 9310119Snilay@cs.wisc.edu # Set the cache line size for the entire system 9410119Snilay@cs.wisc.edu test_sys.cache_line_size = options.cacheline_size 959665Sandreas.hansson@arm.com 9610119Snilay@cs.wisc.edu # Create a top-level voltage domain 9710119Snilay@cs.wisc.edu test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 9810119Snilay@cs.wisc.edu 9910119Snilay@cs.wisc.edu # Create a source clock for the system and set the clock period 10010119Snilay@cs.wisc.edu test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 10110119Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 10210119Snilay@cs.wisc.edu 10310119Snilay@cs.wisc.edu # Create a CPU voltage domain 10410119Snilay@cs.wisc.edu test_sys.cpu_voltage_domain = VoltageDomain() 10510119Snilay@cs.wisc.edu 10610119Snilay@cs.wisc.edu # Create a source clock for the CPUs and set the clock period 10710119Snilay@cs.wisc.edu test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 10810119Snilay@cs.wisc.edu voltage_domain = 10910119Snilay@cs.wisc.edu test_sys.cpu_voltage_domain) 11010119Snilay@cs.wisc.edu 11110119Snilay@cs.wisc.edu if options.kernel is not None: 11210119Snilay@cs.wisc.edu test_sys.kernel = binary(options.kernel) 11310119Snilay@cs.wisc.edu 11410119Snilay@cs.wisc.edu if options.script is not None: 11510119Snilay@cs.wisc.edu test_sys.readfile = options.script 11610119Snilay@cs.wisc.edu 11710119Snilay@cs.wisc.edu if options.lpae: 11810119Snilay@cs.wisc.edu test_sys.have_lpae = True 11910119Snilay@cs.wisc.edu 12010119Snilay@cs.wisc.edu if options.virtualisation: 12110119Snilay@cs.wisc.edu test_sys.have_virtualization = True 12210119Snilay@cs.wisc.edu 12310119Snilay@cs.wisc.edu test_sys.init_param = options.init_param 12410119Snilay@cs.wisc.edu 12510119Snilay@cs.wisc.edu # For now, assign all the CPUs to the same clock domain 12610119Snilay@cs.wisc.edu test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 12710119Snilay@cs.wisc.edu for i in xrange(np)] 12810119Snilay@cs.wisc.edu 12910119Snilay@cs.wisc.edu if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 13010119Snilay@cs.wisc.edu test_sys.vm = KvmVM() 13110119Snilay@cs.wisc.edu 13210119Snilay@cs.wisc.edu if options.ruby: 13310119Snilay@cs.wisc.edu # Check for timing mode because ruby does not support atomic accesses 13410119Snilay@cs.wisc.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 13510119Snilay@cs.wisc.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 13610119Snilay@cs.wisc.edu sys.exit(1) 13710119Snilay@cs.wisc.edu 13810119Snilay@cs.wisc.edu Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports) 13910119Snilay@cs.wisc.edu 14010119Snilay@cs.wisc.edu # Create a seperate clock domain for Ruby 14110119Snilay@cs.wisc.edu test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 14210119Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 14310119Snilay@cs.wisc.edu 14410119Snilay@cs.wisc.edu for (i, cpu) in enumerate(test_sys.cpu): 14510119Snilay@cs.wisc.edu # 14610119Snilay@cs.wisc.edu # Tie the cpu ports to the correct ruby system ports 14710119Snilay@cs.wisc.edu # 14810119Snilay@cs.wisc.edu cpu.clk_domain = test_sys.cpu_clk_domain 14910119Snilay@cs.wisc.edu cpu.createThreads() 15010119Snilay@cs.wisc.edu cpu.createInterruptController() 15110119Snilay@cs.wisc.edu 15210119Snilay@cs.wisc.edu cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave 15310119Snilay@cs.wisc.edu cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave 15410119Snilay@cs.wisc.edu 15510119Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "x86": 15610119Snilay@cs.wisc.edu cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 15710119Snilay@cs.wisc.edu cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 15810119Snilay@cs.wisc.edu 15910119Snilay@cs.wisc.edu cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master 16010119Snilay@cs.wisc.edu cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave 16110119Snilay@cs.wisc.edu cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master 16210119Snilay@cs.wisc.edu 16310119Snilay@cs.wisc.edu test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True 16410119Snilay@cs.wisc.edu 16510119Snilay@cs.wisc.edu # Create the appropriate memory controllers 16610119Snilay@cs.wisc.edu # and connect them to the IO bus 16710119Snilay@cs.wisc.edu test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] 16810119Snilay@cs.wisc.edu for i in xrange(len(test_sys.mem_ctrls)): 16910119Snilay@cs.wisc.edu test_sys.mem_ctrls[i].port = test_sys.iobus.master 17010119Snilay@cs.wisc.edu 1712995SN/A else: 17210119Snilay@cs.wisc.edu if options.caches or options.l2cache: 17310119Snilay@cs.wisc.edu # By default the IOCache runs at the system clock 17410119Snilay@cs.wisc.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 17510119Snilay@cs.wisc.edu test_sys.iocache.cpu_side = test_sys.iobus.master 17610119Snilay@cs.wisc.edu test_sys.iocache.mem_side = test_sys.membus.slave 17710119Snilay@cs.wisc.edu else: 17810119Snilay@cs.wisc.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 17910119Snilay@cs.wisc.edu test_sys.iobridge.slave = test_sys.iobus.master 18010119Snilay@cs.wisc.edu test_sys.iobridge.master = test_sys.membus.slave 1813304Sstever@eecs.umich.edu 18210119Snilay@cs.wisc.edu # Sanity check 18310119Snilay@cs.wisc.edu if options.fastmem: 18410119Snilay@cs.wisc.edu if TestCPUClass != AtomicSimpleCPU: 18510119Snilay@cs.wisc.edu fatal("Fastmem can only be used with atomic CPU!") 18610119Snilay@cs.wisc.edu if (options.caches or options.l2cache): 18710119Snilay@cs.wisc.edu fatal("You cannot use fastmem in combination with caches!") 1886135Sgblack@eecs.umich.edu 18910119Snilay@cs.wisc.edu for i in xrange(np): 19010119Snilay@cs.wisc.edu if options.fastmem: 19110119Snilay@cs.wisc.edu test_sys.cpu[i].fastmem = True 19210119Snilay@cs.wisc.edu if options.checker: 19310119Snilay@cs.wisc.edu test_sys.cpu[i].addCheckerCpu() 19410119Snilay@cs.wisc.edu test_sys.cpu[i].createThreads() 1953819Shsul@eecs.umich.edu 19610119Snilay@cs.wisc.edu CacheConfig.config_cache(options, test_sys) 19710119Snilay@cs.wisc.edu MemConfig.config_mem(options, test_sys) 19810118Snilay@cs.wisc.edu 19910119Snilay@cs.wisc.edu return test_sys 2009827Sakash.bagdia@arm.com 20110119Snilay@cs.wisc.edudef build_drive_system(np): 20210119Snilay@cs.wisc.edu # driver system CPU is always simple, so is the memory 20310119Snilay@cs.wisc.edu # Note this is an assignment of a class, not an instance. 20410119Snilay@cs.wisc.edu DriveCPUClass = AtomicSimpleCPU 20510119Snilay@cs.wisc.edu drive_mem_mode = 'atomic' 20610119Snilay@cs.wisc.edu DriveMemClass = SimpleMemory 2079827Sakash.bagdia@arm.com 2086654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'alpha': 2099826Sandreas.hansson@arm.com drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 2106654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 2119826Sandreas.hansson@arm.com drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 2126654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'sparc': 2139826Sandreas.hansson@arm.com drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 2146654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 21510056Snilay@cs.wisc.edu drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1]) 2167586SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 2179826Sandreas.hansson@arm.com drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 2188661SAli.Saidi@ARM.com 2199827Sakash.bagdia@arm.com # Create a top-level voltage domain 2209827Sakash.bagdia@arm.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 2219827Sakash.bagdia@arm.com 2229793Sakash.bagdia@arm.com # Create a source clock for the system and set the clock period 22310119Snilay@cs.wisc.edu drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 22410119Snilay@cs.wisc.edu voltage_domain = drive_sys.voltage_domain) 2259790Sakash.bagdia@arm.com 2269827Sakash.bagdia@arm.com # Create a CPU voltage domain 2279827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain = VoltageDomain() 2289827Sakash.bagdia@arm.com 2299793Sakash.bagdia@arm.com # Create a source clock for the CPUs and set the clock period 2309827Sakash.bagdia@arm.com drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2319827Sakash.bagdia@arm.com voltage_domain = 2329827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain) 2339793Sakash.bagdia@arm.com 2349793Sakash.bagdia@arm.com drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2359793Sakash.bagdia@arm.com cpu_id=0) 2369384SAndreas.Sandberg@arm.com drive_sys.cpu.createThreads() 2378863Snilay@cs.wisc.edu drive_sys.cpu.createInterruptController() 2387876Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2394968Sacolyte@umich.edu if options.fastmem: 2408926Sandreas.hansson@arm.com drive_sys.cpu.fastmem = True 2414837Ssaidi@eecs.umich.edu if options.kernel is not None: 2424837Ssaidi@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2439408Sandreas.hansson@arm.com 2449653SAndreas.Sandberg@ARM.com if is_kvm_cpu(DriveCPUClass): 2459653SAndreas.Sandberg@ARM.com drive_sys.vm = KvmVM() 2469653SAndreas.Sandberg@ARM.com 2479164Sandreas.hansson@arm.com drive_sys.iobridge = Bridge(delay='50ns', 2489408Sandreas.hansson@arm.com ranges = drive_sys.mem_ranges) 2498845Sandreas.hansson@arm.com drive_sys.iobridge.slave = drive_sys.iobus.master 2508845Sandreas.hansson@arm.com drive_sys.iobridge.master = drive_sys.membus.slave 2514837Ssaidi@eecs.umich.edu 2529826Sandreas.hansson@arm.com # Create the appropriate memory controllers and connect them to the 2539826Sandreas.hansson@arm.com # memory bus 2549835Sandreas.hansson@arm.com drive_sys.mem_ctrls = [DriveMemClass(range = r) 2559826Sandreas.hansson@arm.com for r in drive_sys.mem_ranges] 2569826Sandreas.hansson@arm.com for i in xrange(len(drive_sys.mem_ctrls)): 2579826Sandreas.hansson@arm.com drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2589826Sandreas.hansson@arm.com 2598659SAli.Saidi@ARM.com drive_sys.init_param = options.init_param 26010119Snilay@cs.wisc.edu 26110119Snilay@cs.wisc.edu return drive_sys 26210119Snilay@cs.wisc.edu 26310119Snilay@cs.wisc.edu# Add options 26410119Snilay@cs.wisc.eduparser = optparse.OptionParser() 26510119Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 26610119Snilay@cs.wisc.eduOptions.addFSOptions(parser) 26710119Snilay@cs.wisc.edu 26810119Snilay@cs.wisc.edu# Add the ruby specific and protocol specific options 26910119Snilay@cs.wisc.eduif '--ruby' in sys.argv: 27010119Snilay@cs.wisc.edu Ruby.define_options(parser) 27110119Snilay@cs.wisc.edu 27210119Snilay@cs.wisc.edu(options, args) = parser.parse_args() 27310119Snilay@cs.wisc.edu 27410119Snilay@cs.wisc.eduif args: 27510119Snilay@cs.wisc.edu print "Error: script doesn't take any positional arguments" 27610119Snilay@cs.wisc.edu sys.exit(1) 27710119Snilay@cs.wisc.edu 27810119Snilay@cs.wisc.edu# system under test can be any CPU 27910119Snilay@cs.wisc.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 28010119Snilay@cs.wisc.edu 28110119Snilay@cs.wisc.edu# Match the memories with the CPUs, based on the options for the test system 28210119Snilay@cs.wisc.eduTestMemClass = Simulation.setMemClass(options) 28310119Snilay@cs.wisc.edu 28410119Snilay@cs.wisc.eduif options.benchmark: 28510119Snilay@cs.wisc.edu try: 28610119Snilay@cs.wisc.edu bm = Benchmarks[options.benchmark] 28710119Snilay@cs.wisc.edu except KeyError: 28810119Snilay@cs.wisc.edu print "Error benchmark %s has not been defined." % options.benchmark 28910119Snilay@cs.wisc.edu print "Valid benchmarks are: %s" % DefinedBenchmarks 29010119Snilay@cs.wisc.edu sys.exit(1) 29110119Snilay@cs.wisc.eduelse: 29210119Snilay@cs.wisc.edu if options.dual: 29310119Snilay@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), 29410119Snilay@cs.wisc.edu SysConfig(disk=options.disk_image, mem=options.mem_size)] 29510119Snilay@cs.wisc.edu else: 29610119Snilay@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 29710119Snilay@cs.wisc.edu 29810119Snilay@cs.wisc.edunp = options.num_cpus 29910119Snilay@cs.wisc.edu 30010119Snilay@cs.wisc.edutest_sys = build_test_system(np) 30110119Snilay@cs.wisc.eduif len(bm) == 2: 30210119Snilay@cs.wisc.edu drive_sys = build_drive_system(np) 3038801Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 3043005Sstever@eecs.umich.eduelif len(bm) == 1: 3058801Sgblack@eecs.umich.edu root = Root(full_system=True, system=test_sys) 3063005Sstever@eecs.umich.eduelse: 3073005Sstever@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 3083005Sstever@eecs.umich.edu sys.exit(1) 3092566SN/A 3107861Sgblack@eecs.umich.eduif options.timesync: 3117861Sgblack@eecs.umich.edu root.time_sync_enable = True 3127861Sgblack@eecs.umich.edu 3138635Schris.emmons@arm.comif options.frame_capture: 3148635Schris.emmons@arm.com VncServer.frame_capture = True 3158635Schris.emmons@arm.com 3169061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options) 3173481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 318