fs.py revision 10118
12553SN/A# Copyright (c) 2010-2013 ARM Limited 22553SN/A# All rights reserved. 32553SN/A# 42553SN/A# The license below extends only to copyright in the software and shall 52553SN/A# not be construed as granting a license to any other intellectual 62553SN/A# property including but not limited to intellectual property relating 72553SN/A# to a hardware implementation of the functionality of the software 82553SN/A# licensed hereunder. You may use the software subject to the license 92553SN/A# terms below provided that you ensure that this notice is replicated 102553SN/A# unmodified and in its entirety in all distributions of the software, 112553SN/A# modified or unmodified, in source code or in binary form. 122553SN/A# 132553SN/A# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 142553SN/A# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 152553SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 162553SN/A# All rights reserved. 172553SN/A# 182553SN/A# Redistribution and use in source and binary forms, with or without 192553SN/A# modification, are permitted provided that the following conditions are 202553SN/A# met: redistributions of source code must retain the above copyright 212553SN/A# notice, this list of conditions and the following disclaimer; 222553SN/A# redistributions in binary form must reproduce the above copyright 232553SN/A# notice, this list of conditions and the following disclaimer in the 242553SN/A# documentation and/or other materials provided with the distribution; 252553SN/A# neither the name of the copyright holders nor the names of its 262553SN/A# contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu# this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu# 292553SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302553SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315569Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325569Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332553SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342553SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352553SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362553SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372553SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382553SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392553SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402553SN/A# 412553SN/A# Authors: Ali Saidi 422553SN/A# Brad Beckmann 432553SN/A 442553SN/Aimport optparse 452553SN/Aimport sys 462553SN/A 472553SN/Aimport m5 482553SN/Afrom m5.defines import buildEnv 492553SN/Afrom m5.objects import * 502553SN/Afrom m5.util import addToPath, fatal 512553SN/A 522553SN/AaddToPath('../common') 535543Ssaidi@eecs.umich.eduaddToPath('../ruby') 545543Ssaidi@eecs.umich.edu 555543Ssaidi@eecs.umich.eduimport Ruby 565543Ssaidi@eecs.umich.edu 575543Ssaidi@eecs.umich.edufrom FSConfig import * 585543Ssaidi@eecs.umich.edufrom SysPaths import * 595543Ssaidi@eecs.umich.edufrom Benchmarks import * 605543Ssaidi@eecs.umich.eduimport Simulation 615543Ssaidi@eecs.umich.eduimport CacheConfig 625543Ssaidi@eecs.umich.eduimport MemConfig 635543Ssaidi@eecs.umich.edufrom Caches import * 645543Ssaidi@eecs.umich.eduimport Options 655543Ssaidi@eecs.umich.edu 665543Ssaidi@eecs.umich.eduparser = optparse.OptionParser() 675543Ssaidi@eecs.umich.eduOptions.addCommonOptions(parser) 682553SN/AOptions.addFSOptions(parser) 692553SN/A 702553SN/A# Add the ruby specific and protocol specific options 712553SN/Aif '--ruby' in sys.argv: 728600Ssteve.reinhardt@amd.com Ruby.define_options(parser) 732553SN/A 742553SN/A(options, args) = parser.parse_args() 752553SN/A 765569Snate@binkert.orgif args: 775569Snate@binkert.org print "Error: script doesn't take any positional arguments" 785569Snate@binkert.org sys.exit(1) 795569Snate@binkert.org 805569Snate@binkert.org# driver system CPU is always simple... note this is an assignment of 815569Snate@binkert.org# a class, not an instance. 825569Snate@binkert.orgDriveCPUClass = AtomicSimpleCPU 832555SN/Adrive_mem_mode = 'atomic' 842553SN/A 852553SN/A# Check if KVM support has been enabled, we might need to do VM 862553SN/A# configuration if that's the case. 872553SN/Ahave_kvm_support = 'BaseKvmCPU' in globals() 882553SN/Adef is_kvm_cpu(cpu_class): 892553SN/A return have_kvm_support and cpu_class != None and \ 902553SN/A issubclass(cpu_class, BaseKvmCPU) 912553SN/A 922553SN/A# system under test can be any CPU 939141Smarc.orr@gmail.com(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 949141Smarc.orr@gmail.com 959141Smarc.orr@gmail.com# Match the memories with the CPUs, the driver system always simple, 969141Smarc.orr@gmail.com# and based on the options for the test system 979141Smarc.orr@gmail.comDriveMemClass = SimpleMemory 989141Smarc.orr@gmail.comTestMemClass = Simulation.setMemClass(options) 999141Smarc.orr@gmail.com 1009141Smarc.orr@gmail.comif options.benchmark: 1019141Smarc.orr@gmail.com try: 1022553SN/A bm = Benchmarks[options.benchmark] 1032553SN/A except KeyError: 1049141Smarc.orr@gmail.com print "Error benchmark %s has not been defined." % options.benchmark 1059141Smarc.orr@gmail.com print "Valid benchmarks are: %s" % DefinedBenchmarks 1069141Smarc.orr@gmail.com sys.exit(1) 1079141Smarc.orr@gmail.comelse: 1089141Smarc.orr@gmail.com if options.dual: 1099141Smarc.orr@gmail.com bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), 1109141Smarc.orr@gmail.com SysConfig(disk=options.disk_image, mem=options.mem_size)] 1119141Smarc.orr@gmail.com else: 1129141Smarc.orr@gmail.com bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 1139141Smarc.orr@gmail.com 1149141Smarc.orr@gmail.comnp = options.num_cpus 1159141Smarc.orr@gmail.com 1169141Smarc.orr@gmail.comif buildEnv['TARGET_ISA'] == "alpha": 1179141Smarc.orr@gmail.com test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby) 1189141Smarc.orr@gmail.comelif buildEnv['TARGET_ISA'] == "mips": 1199141Smarc.orr@gmail.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 1209141Smarc.orr@gmail.comelif buildEnv['TARGET_ISA'] == "sparc": 1219141Smarc.orr@gmail.com test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1222553SN/Aelif buildEnv['TARGET_ISA'] == "x86": 1232553SN/A test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 1242555SN/A options.ruby) 1259146Smarc.orr@gmail.comelif buildEnv['TARGET_ISA'] == "arm": 1269146Smarc.orr@gmail.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 1279146Smarc.orr@gmail.com options.dtb_filename, 1289146Smarc.orr@gmail.com bare_metal=options.bare_metal) 1299146Smarc.orr@gmail.com if options.enable_context_switch_stats_dump: 13011320Ssteve.reinhardt@amd.com test_sys.enable_context_switch_stats_dump = True 1316640Svince@csl.cornell.eduelse: 1326640Svince@csl.cornell.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1336640Svince@csl.cornell.edu 1346640Svince@csl.cornell.edu# Set the cache line size for the entire system 1356640Svince@csl.cornell.edutest_sys.cache_line_size = options.cacheline_size 1366640Svince@csl.cornell.edu 1376640Svince@csl.cornell.edu# Create a top-level voltage domain 1386640Svince@csl.cornell.edutest_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1396640Svince@csl.cornell.edu 1406640Svince@csl.cornell.edu# Create a source clock for the system and set the clock period 1416640Svince@csl.cornell.edutest_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1426640Svince@csl.cornell.edu voltage_domain = test_sys.voltage_domain) 1436640Svince@csl.cornell.edu 1446640Svince@csl.cornell.edu# Create a CPU voltage domain 1459112Smarc.orr@gmail.comtest_sys.cpu_voltage_domain = VoltageDomain() 1469112Smarc.orr@gmail.com 1479112Smarc.orr@gmail.com# Create a source clock for the CPUs and set the clock period 1489112Smarc.orr@gmail.comtest_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1492553SN/A voltage_domain = 1502553SN/A test_sys.cpu_voltage_domain) 1515569Snate@binkert.org 152if options.kernel is not None: 153 test_sys.kernel = binary(options.kernel) 154 155if options.script is not None: 156 test_sys.readfile = options.script 157 158if options.lpae: 159 test_sys.have_lpae = True 160 161if options.virtualisation: 162 test_sys.have_virtualization = True 163 164test_sys.init_param = options.init_param 165 166# For now, assign all the CPUs to the same clock domain 167test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 168 for i in xrange(np)] 169 170if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 171 test_sys.vm = KvmVM() 172 173if options.ruby: 174 # Check for timing mode because ruby does not support atomic accesses 175 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 176 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 177 sys.exit(1) 178 179 Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports) 180 181 # Create a seperate clock domain for Ruby 182 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 183 voltage_domain = test_sys.voltage_domain) 184 185 for (i, cpu) in enumerate(test_sys.cpu): 186 # 187 # Tie the cpu ports to the correct ruby system ports 188 # 189 cpu.clk_domain = test_sys.cpu_clk_domain 190 cpu.createThreads() 191 cpu.createInterruptController() 192 193 cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave 194 cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave 195 196 if buildEnv['TARGET_ISA'] == "x86": 197 cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 198 cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 199 200 cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master 201 cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave 202 cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master 203 204 test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True 205 206 # Create the appropriate memory controllers and connect them to the 207 # PIO bus 208 test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] 209 for i in xrange(len(test_sys.mem_ctrls)): 210 test_sys.mem_ctrls[i].port = test_sys.iobus.master 211 212else: 213 if options.caches or options.l2cache: 214 # By default the IOCache runs at the system clock 215 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 216 test_sys.iocache.cpu_side = test_sys.iobus.master 217 test_sys.iocache.mem_side = test_sys.membus.slave 218 else: 219 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 220 test_sys.iobridge.slave = test_sys.iobus.master 221 test_sys.iobridge.master = test_sys.membus.slave 222 223 # Sanity check 224 if options.fastmem: 225 if TestCPUClass != AtomicSimpleCPU: 226 fatal("Fastmem can only be used with atomic CPU!") 227 if (options.caches or options.l2cache): 228 fatal("You cannot use fastmem in combination with caches!") 229 230 for i in xrange(np): 231 if options.fastmem: 232 test_sys.cpu[i].fastmem = True 233 if options.checker: 234 test_sys.cpu[i].addCheckerCpu() 235 test_sys.cpu[i].createThreads() 236 237 CacheConfig.config_cache(options, test_sys) 238 MemConfig.config_mem(options, test_sys) 239 240if len(bm) == 2: 241 if buildEnv['TARGET_ISA'] == 'alpha': 242 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 243 elif buildEnv['TARGET_ISA'] == 'mips': 244 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 245 elif buildEnv['TARGET_ISA'] == 'sparc': 246 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 247 elif buildEnv['TARGET_ISA'] == 'x86': 248 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1]) 249 elif buildEnv['TARGET_ISA'] == 'arm': 250 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 251 252 # Create a top-level voltage domain 253 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 254 255 # Create a source clock for the system and set the clock period 256 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) 257 258 # Create a CPU voltage domain 259 drive_sys.cpu_voltage_domain = VoltageDomain() 260 261 # Create a source clock for the CPUs and set the clock period 262 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 263 voltage_domain = 264 drive_sys.cpu_voltage_domain) 265 266 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 267 cpu_id=0) 268 drive_sys.cpu.createThreads() 269 drive_sys.cpu.createInterruptController() 270 drive_sys.cpu.connectAllPorts(drive_sys.membus) 271 if options.fastmem: 272 drive_sys.cpu.fastmem = True 273 if options.kernel is not None: 274 drive_sys.kernel = binary(options.kernel) 275 276 if is_kvm_cpu(DriveCPUClass): 277 drive_sys.vm = KvmVM() 278 279 drive_sys.iobridge = Bridge(delay='50ns', 280 ranges = drive_sys.mem_ranges) 281 drive_sys.iobridge.slave = drive_sys.iobus.master 282 drive_sys.iobridge.master = drive_sys.membus.slave 283 284 # Create the appropriate memory controllers and connect them to the 285 # memory bus 286 drive_sys.mem_ctrls = [DriveMemClass(range = r) 287 for r in drive_sys.mem_ranges] 288 for i in xrange(len(drive_sys.mem_ctrls)): 289 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 290 291 drive_sys.init_param = options.init_param 292 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 293elif len(bm) == 1: 294 root = Root(full_system=True, system=test_sys) 295else: 296 print "Error I don't know how to create more than 2 systems." 297 sys.exit(1) 298 299if options.timesync: 300 root.time_sync_enable = True 301 302if options.frame_capture: 303 VncServer.frame_capture = True 304 305Simulation.setWorkCountOptions(test_sys, options) 306Simulation.run(options, root, test_sys, FutureClass) 307