fs.py revision 10118
19793Sakash.bagdia@arm.com# Copyright (c) 2010-2013 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 1310118Snilay@cs.wisc.edu# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 1410118Snilay@cs.wisc.edu# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 153970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 163005Sstever@eecs.umich.edu# All rights reserved. 173005Sstever@eecs.umich.edu# 183005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 193005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 203005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 223005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 233005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 243005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 253005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 263005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 273005Sstever@eecs.umich.edu# this software without specific prior written permission. 283005Sstever@eecs.umich.edu# 293005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 303005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403005Sstever@eecs.umich.edu# 413005Sstever@eecs.umich.edu# Authors: Ali Saidi 4210118Snilay@cs.wisc.edu# Brad Beckmann 433005Sstever@eecs.umich.edu 446654Snate@binkert.orgimport optparse 456654Snate@binkert.orgimport sys 462889SN/A 472710SN/Aimport m5 486654Snate@binkert.orgfrom m5.defines import buildEnv 496654Snate@binkert.orgfrom m5.objects import * 506654Snate@binkert.orgfrom m5.util import addToPath, fatal 515457Ssaidi@eecs.umich.edu 526654Snate@binkert.orgaddToPath('../common') 5310118Snilay@cs.wisc.eduaddToPath('../ruby') 5410118Snilay@cs.wisc.edu 5510118Snilay@cs.wisc.eduimport Ruby 566654Snate@binkert.org 572934SN/Afrom FSConfig import * 582549SN/Afrom SysPaths import * 592995SN/Afrom Benchmarks import * 603395Shsul@eecs.umich.eduimport Simulation 616981SLisa.Hsu@amd.comimport CacheConfig 629836Sandreas.hansson@arm.comimport MemConfig 633448Shsul@eecs.umich.edufrom Caches import * 648920Snilay@cs.wisc.eduimport Options 653444Sktlim@umich.edu 662889SN/Aparser = optparse.OptionParser() 678920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 688920Snilay@cs.wisc.eduOptions.addFSOptions(parser) 693322Shsul@eecs.umich.edu 7010118Snilay@cs.wisc.edu# Add the ruby specific and protocol specific options 7110118Snilay@cs.wisc.eduif '--ruby' in sys.argv: 7210118Snilay@cs.wisc.edu Ruby.define_options(parser) 7310118Snilay@cs.wisc.edu 742710SN/A(options, args) = parser.parse_args() 752710SN/A 762710SN/Aif args: 772710SN/A print "Error: script doesn't take any positional arguments" 782710SN/A sys.exit(1) 792710SN/A 803322Shsul@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of 813304Sstever@eecs.umich.edu# a class, not an instance. 823322Shsul@eecs.umich.eduDriveCPUClass = AtomicSimpleCPU 833322Shsul@eecs.umich.edudrive_mem_mode = 'atomic' 843304Sstever@eecs.umich.edu 859653SAndreas.Sandberg@ARM.com# Check if KVM support has been enabled, we might need to do VM 869653SAndreas.Sandberg@ARM.com# configuration if that's the case. 879653SAndreas.Sandberg@ARM.comhave_kvm_support = 'BaseKvmCPU' in globals() 889653SAndreas.Sandberg@ARM.comdef is_kvm_cpu(cpu_class): 899653SAndreas.Sandberg@ARM.com return have_kvm_support and cpu_class != None and \ 909653SAndreas.Sandberg@ARM.com issubclass(cpu_class, BaseKvmCPU) 919653SAndreas.Sandberg@ARM.com 923481Shsul@eecs.umich.edu# system under test can be any CPU 933481Shsul@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 942566SN/A 959665Sandreas.hansson@arm.com# Match the memories with the CPUs, the driver system always simple, 969665Sandreas.hansson@arm.com# and based on the options for the test system 979665Sandreas.hansson@arm.comDriveMemClass = SimpleMemory 989665Sandreas.hansson@arm.comTestMemClass = Simulation.setMemClass(options) 999665Sandreas.hansson@arm.com 1002995SN/Aif options.benchmark: 1013304Sstever@eecs.umich.edu try: 1023304Sstever@eecs.umich.edu bm = Benchmarks[options.benchmark] 1033304Sstever@eecs.umich.edu except KeyError: 1042995SN/A print "Error benchmark %s has not been defined." % options.benchmark 1052995SN/A print "Valid benchmarks are: %s" % DefinedBenchmarks 1062995SN/A sys.exit(1) 1072917SN/Aelse: 1082995SN/A if options.dual: 10910041Snilay@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), 11010041Snilay@cs.wisc.edu SysConfig(disk=options.disk_image, mem=options.mem_size)] 1112995SN/A else: 1128956Sjayneel@cs.wisc.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 1133304Sstever@eecs.umich.edu 1146135Sgblack@eecs.umich.edunp = options.num_cpus 1156135Sgblack@eecs.umich.edu 1166654Snate@binkert.orgif buildEnv['TARGET_ISA'] == "alpha": 11710118Snilay@cs.wisc.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby) 1186654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "mips": 1199826Sandreas.hansson@arm.com test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 1206654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "sparc": 1219826Sandreas.hansson@arm.com test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1226654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "x86": 12310118Snilay@cs.wisc.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 12410118Snilay@cs.wisc.edu options.ruby) 1257586SAli.Saidi@arm.comelif buildEnv['TARGET_ISA'] == "arm": 1269826Sandreas.hansson@arm.com test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 1279826Sandreas.hansson@arm.com options.dtb_filename, 1289665Sandreas.hansson@arm.com bare_metal=options.bare_metal) 1299935Sdam.sunwoo@arm.com if options.enable_context_switch_stats_dump: 1309935Sdam.sunwoo@arm.com test_sys.enable_context_switch_stats_dump = True 1313819Shsul@eecs.umich.eduelse: 1329059Snilay@cs.wisc.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1333819Shsul@eecs.umich.edu 13410118Snilay@cs.wisc.edu# Set the cache line size for the entire system 13510118Snilay@cs.wisc.edutest_sys.cache_line_size = options.cacheline_size 13610118Snilay@cs.wisc.edu 1379827Sakash.bagdia@arm.com# Create a top-level voltage domain 1389827Sakash.bagdia@arm.comtest_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1399827Sakash.bagdia@arm.com 1409793Sakash.bagdia@arm.com# Create a source clock for the system and set the clock period 1419827Sakash.bagdia@arm.comtest_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 1429827Sakash.bagdia@arm.com voltage_domain = test_sys.voltage_domain) 1439827Sakash.bagdia@arm.com 1449827Sakash.bagdia@arm.com# Create a CPU voltage domain 1459827Sakash.bagdia@arm.comtest_sys.cpu_voltage_domain = VoltageDomain() 1469793Sakash.bagdia@arm.com 1479793Sakash.bagdia@arm.com# Create a source clock for the CPUs and set the clock period 1489827Sakash.bagdia@arm.comtest_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 1499827Sakash.bagdia@arm.com voltage_domain = 1509827Sakash.bagdia@arm.com test_sys.cpu_voltage_domain) 1519790Sakash.bagdia@arm.com 1523873Sbinkertn@umich.eduif options.kernel is not None: 1533873Sbinkertn@umich.edu test_sys.kernel = binary(options.kernel) 1543873Sbinkertn@umich.edu 1553873Sbinkertn@umich.eduif options.script is not None: 1563873Sbinkertn@umich.edu test_sys.readfile = options.script 1573873Sbinkertn@umich.edu 15810037SARM gem5 Developersif options.lpae: 15910037SARM gem5 Developers test_sys.have_lpae = True 16010037SARM gem5 Developers 16110037SARM gem5 Developersif options.virtualisation: 16210037SARM gem5 Developers test_sys.have_virtualization = True 16310037SARM gem5 Developers 1648659SAli.Saidi@ARM.comtest_sys.init_param = options.init_param 1658659SAli.Saidi@ARM.com 1669793Sakash.bagdia@arm.com# For now, assign all the CPUs to the same clock domain 1679793Sakash.bagdia@arm.comtest_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 1689793Sakash.bagdia@arm.com for i in xrange(np)] 1693668Srdreslin@umich.edu 1709653SAndreas.Sandberg@ARM.comif is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1719653SAndreas.Sandberg@ARM.com test_sys.vm = KvmVM() 1729653SAndreas.Sandberg@ARM.com 17310118Snilay@cs.wisc.eduif options.ruby: 17410118Snilay@cs.wisc.edu # Check for timing mode because ruby does not support atomic accesses 17510118Snilay@cs.wisc.edu if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 17610118Snilay@cs.wisc.edu print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 17710118Snilay@cs.wisc.edu sys.exit(1) 17810118Snilay@cs.wisc.edu 17910118Snilay@cs.wisc.edu Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports) 18010118Snilay@cs.wisc.edu 18110118Snilay@cs.wisc.edu # Create a seperate clock domain for Ruby 18210118Snilay@cs.wisc.edu test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 18310118Snilay@cs.wisc.edu voltage_domain = test_sys.voltage_domain) 18410118Snilay@cs.wisc.edu 18510118Snilay@cs.wisc.edu for (i, cpu) in enumerate(test_sys.cpu): 18610118Snilay@cs.wisc.edu # 18710118Snilay@cs.wisc.edu # Tie the cpu ports to the correct ruby system ports 18810118Snilay@cs.wisc.edu # 18910118Snilay@cs.wisc.edu cpu.clk_domain = test_sys.cpu_clk_domain 19010118Snilay@cs.wisc.edu cpu.createThreads() 19110118Snilay@cs.wisc.edu cpu.createInterruptController() 19210118Snilay@cs.wisc.edu 19310118Snilay@cs.wisc.edu cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave 19410118Snilay@cs.wisc.edu cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave 19510118Snilay@cs.wisc.edu 19610118Snilay@cs.wisc.edu if buildEnv['TARGET_ISA'] == "x86": 19710118Snilay@cs.wisc.edu cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 19810118Snilay@cs.wisc.edu cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 19910118Snilay@cs.wisc.edu 20010118Snilay@cs.wisc.edu cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master 20110118Snilay@cs.wisc.edu cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave 20210118Snilay@cs.wisc.edu cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master 20310118Snilay@cs.wisc.edu 20410118Snilay@cs.wisc.edu test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True 20510118Snilay@cs.wisc.edu 20610118Snilay@cs.wisc.edu # Create the appropriate memory controllers and connect them to the 20710118Snilay@cs.wisc.edu # PIO bus 20810118Snilay@cs.wisc.edu test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] 20910118Snilay@cs.wisc.edu for i in xrange(len(test_sys.mem_ctrls)): 21010118Snilay@cs.wisc.edu test_sys.mem_ctrls[i].port = test_sys.iobus.master 21110118Snilay@cs.wisc.edu 2128713Sandreas.hansson@arm.comelse: 21310118Snilay@cs.wisc.edu if options.caches or options.l2cache: 21410118Snilay@cs.wisc.edu # By default the IOCache runs at the system clock 21510118Snilay@cs.wisc.edu test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 21610118Snilay@cs.wisc.edu test_sys.iocache.cpu_side = test_sys.iobus.master 21710118Snilay@cs.wisc.edu test_sys.iocache.mem_side = test_sys.membus.slave 21810118Snilay@cs.wisc.edu else: 21910118Snilay@cs.wisc.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 22010118Snilay@cs.wisc.edu test_sys.iobridge.slave = test_sys.iobus.master 22110118Snilay@cs.wisc.edu test_sys.iobridge.master = test_sys.membus.slave 2225142Ssaidi@eecs.umich.edu 22310118Snilay@cs.wisc.edu # Sanity check 22410118Snilay@cs.wisc.edu if options.fastmem: 22510118Snilay@cs.wisc.edu if TestCPUClass != AtomicSimpleCPU: 22610118Snilay@cs.wisc.edu fatal("Fastmem can only be used with atomic CPU!") 22710118Snilay@cs.wisc.edu if (options.caches or options.l2cache): 22810118Snilay@cs.wisc.edu fatal("You cannot use fastmem in combination with caches!") 2298926Sandreas.hansson@arm.com 23010118Snilay@cs.wisc.edu for i in xrange(np): 23110118Snilay@cs.wisc.edu if options.fastmem: 23210118Snilay@cs.wisc.edu test_sys.cpu[i].fastmem = True 23310118Snilay@cs.wisc.edu if options.checker: 23410118Snilay@cs.wisc.edu test_sys.cpu[i].addCheckerCpu() 23510118Snilay@cs.wisc.edu test_sys.cpu[i].createThreads() 2368887Sgeoffrey.blake@arm.com 23710118Snilay@cs.wisc.edu CacheConfig.config_cache(options, test_sys) 23810118Snilay@cs.wisc.edu MemConfig.config_mem(options, test_sys) 2399826Sandreas.hansson@arm.com 2403005Sstever@eecs.umich.eduif len(bm) == 2: 2416654Snate@binkert.org if buildEnv['TARGET_ISA'] == 'alpha': 2429826Sandreas.hansson@arm.com drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 2436654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'mips': 2449826Sandreas.hansson@arm.com drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 2456654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'sparc': 2469826Sandreas.hansson@arm.com drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 2476654Snate@binkert.org elif buildEnv['TARGET_ISA'] == 'x86': 24810056Snilay@cs.wisc.edu drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1]) 2497586SAli.Saidi@arm.com elif buildEnv['TARGET_ISA'] == 'arm': 2509826Sandreas.hansson@arm.com drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 2518661SAli.Saidi@ARM.com 2529827Sakash.bagdia@arm.com # Create a top-level voltage domain 2539827Sakash.bagdia@arm.com drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 2549827Sakash.bagdia@arm.com 2559793Sakash.bagdia@arm.com # Create a source clock for the system and set the clock period 2569793Sakash.bagdia@arm.com drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) 2579790Sakash.bagdia@arm.com 2589827Sakash.bagdia@arm.com # Create a CPU voltage domain 2599827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain = VoltageDomain() 2609827Sakash.bagdia@arm.com 2619793Sakash.bagdia@arm.com # Create a source clock for the CPUs and set the clock period 2629827Sakash.bagdia@arm.com drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 2639827Sakash.bagdia@arm.com voltage_domain = 2649827Sakash.bagdia@arm.com drive_sys.cpu_voltage_domain) 2659793Sakash.bagdia@arm.com 2669793Sakash.bagdia@arm.com drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 2679793Sakash.bagdia@arm.com cpu_id=0) 2689384SAndreas.Sandberg@arm.com drive_sys.cpu.createThreads() 2698863Snilay@cs.wisc.edu drive_sys.cpu.createInterruptController() 2707876Sgblack@eecs.umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 2714968Sacolyte@umich.edu if options.fastmem: 2728926Sandreas.hansson@arm.com drive_sys.cpu.fastmem = True 2734837Ssaidi@eecs.umich.edu if options.kernel is not None: 2744837Ssaidi@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 2759408Sandreas.hansson@arm.com 2769653SAndreas.Sandberg@ARM.com if is_kvm_cpu(DriveCPUClass): 2779653SAndreas.Sandberg@ARM.com drive_sys.vm = KvmVM() 2789653SAndreas.Sandberg@ARM.com 2799164Sandreas.hansson@arm.com drive_sys.iobridge = Bridge(delay='50ns', 2809408Sandreas.hansson@arm.com ranges = drive_sys.mem_ranges) 2818845Sandreas.hansson@arm.com drive_sys.iobridge.slave = drive_sys.iobus.master 2828845Sandreas.hansson@arm.com drive_sys.iobridge.master = drive_sys.membus.slave 2834837Ssaidi@eecs.umich.edu 2849826Sandreas.hansson@arm.com # Create the appropriate memory controllers and connect them to the 2859826Sandreas.hansson@arm.com # memory bus 2869835Sandreas.hansson@arm.com drive_sys.mem_ctrls = [DriveMemClass(range = r) 2879826Sandreas.hansson@arm.com for r in drive_sys.mem_ranges] 2889826Sandreas.hansson@arm.com for i in xrange(len(drive_sys.mem_ctrls)): 2899826Sandreas.hansson@arm.com drive_sys.mem_ctrls[i].port = drive_sys.membus.master 2909826Sandreas.hansson@arm.com 2918659SAli.Saidi@ARM.com drive_sys.init_param = options.init_param 2928801Sgblack@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 2933005Sstever@eecs.umich.eduelif len(bm) == 1: 2948801Sgblack@eecs.umich.edu root = Root(full_system=True, system=test_sys) 2953005Sstever@eecs.umich.eduelse: 2963005Sstever@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 2973005Sstever@eecs.umich.edu sys.exit(1) 2982566SN/A 2997861Sgblack@eecs.umich.eduif options.timesync: 3007861Sgblack@eecs.umich.edu root.time_sync_enable = True 3017861Sgblack@eecs.umich.edu 3028635Schris.emmons@arm.comif options.frame_capture: 3038635Schris.emmons@arm.com VncServer.frame_capture = True 3048635Schris.emmons@arm.com 3059061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options) 3063481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 307