fs.py revision 10041
19793Sakash.bagdia@arm.com# Copyright (c) 2010-2013 ARM Limited
27586SAli.Saidi@arm.com# All rights reserved.
37586SAli.Saidi@arm.com#
47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall
57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual
67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating
77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software
87586SAli.Saidi@arm.com# licensed hereunder.  You may use the software subject to the license
97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated
107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software,
117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form.
127586SAli.Saidi@arm.com#
133970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
143005Sstever@eecs.umich.edu# All rights reserved.
153005Sstever@eecs.umich.edu#
163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution;
233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its
243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
253005Sstever@eecs.umich.edu# this software without specific prior written permission.
263005Sstever@eecs.umich.edu#
273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
383005Sstever@eecs.umich.edu#
393005Sstever@eecs.umich.edu# Authors: Ali Saidi
403005Sstever@eecs.umich.edu
416654Snate@binkert.orgimport optparse
426654Snate@binkert.orgimport sys
432889SN/A
442710SN/Aimport m5
456654Snate@binkert.orgfrom m5.defines import buildEnv
466654Snate@binkert.orgfrom m5.objects import *
476654Snate@binkert.orgfrom m5.util import addToPath, fatal
485457Ssaidi@eecs.umich.edu
496654Snate@binkert.orgaddToPath('../common')
506654Snate@binkert.org
512934SN/Afrom FSConfig import *
522549SN/Afrom SysPaths import *
532995SN/Afrom Benchmarks import *
543395Shsul@eecs.umich.eduimport Simulation
556981SLisa.Hsu@amd.comimport CacheConfig
569836Sandreas.hansson@arm.comimport MemConfig
573448Shsul@eecs.umich.edufrom Caches import *
588920Snilay@cs.wisc.eduimport Options
593444Sktlim@umich.edu
602889SN/Aparser = optparse.OptionParser()
618920Snilay@cs.wisc.eduOptions.addCommonOptions(parser)
628920Snilay@cs.wisc.eduOptions.addFSOptions(parser)
633322Shsul@eecs.umich.edu
642710SN/A(options, args) = parser.parse_args()
652710SN/A
662710SN/Aif args:
672710SN/A    print "Error: script doesn't take any positional arguments"
682710SN/A    sys.exit(1)
692710SN/A
703322Shsul@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of
713304Sstever@eecs.umich.edu# a class, not an instance.
723322Shsul@eecs.umich.eduDriveCPUClass = AtomicSimpleCPU
733322Shsul@eecs.umich.edudrive_mem_mode = 'atomic'
743304Sstever@eecs.umich.edu
759653SAndreas.Sandberg@ARM.com# Check if KVM support has been enabled, we might need to do VM
769653SAndreas.Sandberg@ARM.com# configuration if that's the case.
779653SAndreas.Sandberg@ARM.comhave_kvm_support = 'BaseKvmCPU' in globals()
789653SAndreas.Sandberg@ARM.comdef is_kvm_cpu(cpu_class):
799653SAndreas.Sandberg@ARM.com    return have_kvm_support and cpu_class != None and \
809653SAndreas.Sandberg@ARM.com        issubclass(cpu_class, BaseKvmCPU)
819653SAndreas.Sandberg@ARM.com
823481Shsul@eecs.umich.edu# system under test can be any CPU
833481Shsul@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
842566SN/A
859665Sandreas.hansson@arm.com# Match the memories with the CPUs, the driver system always simple,
869665Sandreas.hansson@arm.com# and based on the options for the test system
879665Sandreas.hansson@arm.comDriveMemClass = SimpleMemory
889665Sandreas.hansson@arm.comTestMemClass = Simulation.setMemClass(options)
899665Sandreas.hansson@arm.com
902995SN/Aif options.benchmark:
913304Sstever@eecs.umich.edu    try:
923304Sstever@eecs.umich.edu        bm = Benchmarks[options.benchmark]
933304Sstever@eecs.umich.edu    except KeyError:
942995SN/A        print "Error benchmark %s has not been defined." % options.benchmark
952995SN/A        print "Valid benchmarks are: %s" % DefinedBenchmarks
962995SN/A        sys.exit(1)
972917SN/Aelse:
982995SN/A    if options.dual:
9910041Snilay@cs.wisc.edu        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
10010041Snilay@cs.wisc.edu              SysConfig(disk=options.disk_image, mem=options.mem_size)]
1012995SN/A    else:
1028956Sjayneel@cs.wisc.edu        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
1033304Sstever@eecs.umich.edu
1046135Sgblack@eecs.umich.edunp = options.num_cpus
1056135Sgblack@eecs.umich.edu
1066654Snate@binkert.orgif buildEnv['TARGET_ISA'] == "alpha":
1079826Sandreas.hansson@arm.com    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
1086654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "mips":
1099826Sandreas.hansson@arm.com    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
1106654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "sparc":
1119826Sandreas.hansson@arm.com    test_sys = makeSparcSystem(test_mem_mode, bm[0])
1126654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "x86":
1139826Sandreas.hansson@arm.com    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
1147586SAli.Saidi@arm.comelif buildEnv['TARGET_ISA'] == "arm":
1159826Sandreas.hansson@arm.com    test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
1169826Sandreas.hansson@arm.com                             options.dtb_filename,
1179665Sandreas.hansson@arm.com                             bare_metal=options.bare_metal)
1189935Sdam.sunwoo@arm.com    if options.enable_context_switch_stats_dump:
1199935Sdam.sunwoo@arm.com        test_sys.enable_context_switch_stats_dump = True
1203819Shsul@eecs.umich.eduelse:
1219059Snilay@cs.wisc.edu    fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
1223819Shsul@eecs.umich.edu
1239827Sakash.bagdia@arm.com# Create a top-level voltage domain
1249827Sakash.bagdia@arm.comtest_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
1259827Sakash.bagdia@arm.com
1269793Sakash.bagdia@arm.com# Create a source clock for the system and set the clock period
1279827Sakash.bagdia@arm.comtest_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
1289827Sakash.bagdia@arm.com                                     voltage_domain = test_sys.voltage_domain)
1299827Sakash.bagdia@arm.com
1309827Sakash.bagdia@arm.com# Create a CPU voltage domain
1319827Sakash.bagdia@arm.comtest_sys.cpu_voltage_domain = VoltageDomain()
1329793Sakash.bagdia@arm.com
1339793Sakash.bagdia@arm.com# Create a source clock for the CPUs and set the clock period
1349827Sakash.bagdia@arm.comtest_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
1359827Sakash.bagdia@arm.com                                         voltage_domain =
1369827Sakash.bagdia@arm.com                                         test_sys.cpu_voltage_domain)
1379790Sakash.bagdia@arm.com
1383873Sbinkertn@umich.eduif options.kernel is not None:
1393873Sbinkertn@umich.edu    test_sys.kernel = binary(options.kernel)
1403873Sbinkertn@umich.edu
1413873Sbinkertn@umich.eduif options.script is not None:
1423873Sbinkertn@umich.edu    test_sys.readfile = options.script
1433873Sbinkertn@umich.edu
14410037SARM gem5 Developersif options.lpae:
14510037SARM gem5 Developers    test_sys.have_lpae = True
14610037SARM gem5 Developers
14710037SARM gem5 Developersif options.virtualisation:
14810037SARM gem5 Developers    test_sys.have_virtualization = True
14910037SARM gem5 Developers
1508659SAli.Saidi@ARM.comtest_sys.init_param = options.init_param
1518659SAli.Saidi@ARM.com
1529793Sakash.bagdia@arm.com# For now, assign all the CPUs to the same clock domain
1539793Sakash.bagdia@arm.comtest_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
1549793Sakash.bagdia@arm.com                for i in xrange(np)]
1553668Srdreslin@umich.edu
1569653SAndreas.Sandberg@ARM.comif is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
1579653SAndreas.Sandberg@ARM.com    test_sys.vm = KvmVM()
1589653SAndreas.Sandberg@ARM.com
1596636Ssteve.reinhardt@amd.comif options.caches or options.l2cache:
1609788Sakash.bagdia@arm.com    # By default the IOCache runs at the system clock
1619788Sakash.bagdia@arm.com    test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
1628839Sandreas.hansson@arm.com    test_sys.iocache.cpu_side = test_sys.iobus.master
1638839Sandreas.hansson@arm.com    test_sys.iocache.mem_side = test_sys.membus.slave
1648713Sandreas.hansson@arm.comelse:
1659408Sandreas.hansson@arm.com    test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
1668839Sandreas.hansson@arm.com    test_sys.iobridge.slave = test_sys.iobus.master
1678839Sandreas.hansson@arm.com    test_sys.iobridge.master = test_sys.membus.slave
1685142Ssaidi@eecs.umich.edu
1698926Sandreas.hansson@arm.com# Sanity check
1709317Sandreas.hansson@arm.comif options.fastmem:
1719317Sandreas.hansson@arm.com    if TestCPUClass != AtomicSimpleCPU:
1729317Sandreas.hansson@arm.com        fatal("Fastmem can only be used with atomic CPU!")
1739317Sandreas.hansson@arm.com    if (options.caches or options.l2cache):
1749317Sandreas.hansson@arm.com        fatal("You cannot use fastmem in combination with caches!")
1758926Sandreas.hansson@arm.com
1763312Sstever@eecs.umich.edufor i in xrange(np):
1774968Sacolyte@umich.edu    if options.fastmem:
1788926Sandreas.hansson@arm.com        test_sys.cpu[i].fastmem = True
1798887Sgeoffrey.blake@arm.com    if options.checker:
1808887Sgeoffrey.blake@arm.com        test_sys.cpu[i].addCheckerCpu()
1819384SAndreas.Sandberg@arm.com    test_sys.cpu[i].createThreads()
1828887Sgeoffrey.blake@arm.com
1838887Sgeoffrey.blake@arm.comCacheConfig.config_cache(options, test_sys)
1849836Sandreas.hansson@arm.comMemConfig.config_mem(options, test_sys)
1859826Sandreas.hansson@arm.com
1863005Sstever@eecs.umich.eduif len(bm) == 2:
1876654Snate@binkert.org    if buildEnv['TARGET_ISA'] == 'alpha':
1889826Sandreas.hansson@arm.com        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
1896654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'mips':
1909826Sandreas.hansson@arm.com        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
1916654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'sparc':
1929826Sandreas.hansson@arm.com        drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
1936654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'x86':
1949826Sandreas.hansson@arm.com        drive_sys = makeX86System(drive_mem_mode, np, bm[1])
1957586SAli.Saidi@arm.com    elif buildEnv['TARGET_ISA'] == 'arm':
1969826Sandreas.hansson@arm.com        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
1978661SAli.Saidi@ARM.com
1989827Sakash.bagdia@arm.com    # Create a top-level voltage domain
1999827Sakash.bagdia@arm.com    drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
2009827Sakash.bagdia@arm.com
2019793Sakash.bagdia@arm.com    # Create a source clock for the system and set the clock period
2029793Sakash.bagdia@arm.com    drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
2039790Sakash.bagdia@arm.com
2049827Sakash.bagdia@arm.com    # Create a CPU voltage domain
2059827Sakash.bagdia@arm.com    drive_sys.cpu_voltage_domain = VoltageDomain()
2069827Sakash.bagdia@arm.com
2079793Sakash.bagdia@arm.com    # Create a source clock for the CPUs and set the clock period
2089827Sakash.bagdia@arm.com    drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
2099827Sakash.bagdia@arm.com                                              voltage_domain =
2109827Sakash.bagdia@arm.com                                              drive_sys.cpu_voltage_domain)
2119793Sakash.bagdia@arm.com
2129793Sakash.bagdia@arm.com    drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
2139793Sakash.bagdia@arm.com                                  cpu_id=0)
2149384SAndreas.Sandberg@arm.com    drive_sys.cpu.createThreads()
2158863Snilay@cs.wisc.edu    drive_sys.cpu.createInterruptController()
2167876Sgblack@eecs.umich.edu    drive_sys.cpu.connectAllPorts(drive_sys.membus)
2174968Sacolyte@umich.edu    if options.fastmem:
2188926Sandreas.hansson@arm.com        drive_sys.cpu.fastmem = True
2194837Ssaidi@eecs.umich.edu    if options.kernel is not None:
2204837Ssaidi@eecs.umich.edu        drive_sys.kernel = binary(options.kernel)
2219408Sandreas.hansson@arm.com
2229653SAndreas.Sandberg@ARM.com    if is_kvm_cpu(DriveCPUClass):
2239653SAndreas.Sandberg@ARM.com        drive_sys.vm = KvmVM()
2249653SAndreas.Sandberg@ARM.com
2259164Sandreas.hansson@arm.com    drive_sys.iobridge = Bridge(delay='50ns',
2269408Sandreas.hansson@arm.com                                ranges = drive_sys.mem_ranges)
2278845Sandreas.hansson@arm.com    drive_sys.iobridge.slave = drive_sys.iobus.master
2288845Sandreas.hansson@arm.com    drive_sys.iobridge.master = drive_sys.membus.slave
2294837Ssaidi@eecs.umich.edu
2309826Sandreas.hansson@arm.com    # Create the appropriate memory controllers and connect them to the
2319826Sandreas.hansson@arm.com    # memory bus
2329835Sandreas.hansson@arm.com    drive_sys.mem_ctrls = [DriveMemClass(range = r)
2339826Sandreas.hansson@arm.com                           for r in drive_sys.mem_ranges]
2349826Sandreas.hansson@arm.com    for i in xrange(len(drive_sys.mem_ctrls)):
2359826Sandreas.hansson@arm.com        drive_sys.mem_ctrls[i].port = drive_sys.membus.master
2369826Sandreas.hansson@arm.com
2378659SAli.Saidi@ARM.com    drive_sys.init_param = options.init_param
2388801Sgblack@eecs.umich.edu    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
2393005Sstever@eecs.umich.eduelif len(bm) == 1:
2408801Sgblack@eecs.umich.edu    root = Root(full_system=True, system=test_sys)
2413005Sstever@eecs.umich.eduelse:
2423005Sstever@eecs.umich.edu    print "Error I don't know how to create more than 2 systems."
2433005Sstever@eecs.umich.edu    sys.exit(1)
2442566SN/A
2457861Sgblack@eecs.umich.eduif options.timesync:
2467861Sgblack@eecs.umich.edu    root.time_sync_enable = True
2477861Sgblack@eecs.umich.edu
2488635Schris.emmons@arm.comif options.frame_capture:
2498635Schris.emmons@arm.com    VncServer.frame_capture = True
2508635Schris.emmons@arm.com
2519061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options)
2523481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass)
253