etrace_replay.py revision 13774:a1be2a0c55f2
112726Snikos.nikoleris@arm.com# Copyright (c) 2015 ARM Limited 29288SN/A# All rights reserved. 39288SN/A# 49288SN/A# The license below extends only to copyright in the software and shall 59288SN/A# not be construed as granting a license to any other intellectual 69288SN/A# property including but not limited to intellectual property relating 79288SN/A# to a hardware implementation of the functionality of the software 89288SN/A# licensed hereunder. You may use the software subject to the license 99288SN/A# terms below provided that you ensure that this notice is replicated 109288SN/A# unmodified and in its entirety in all distributions of the software, 119288SN/A# modified or unmodified, in source code or in binary form. 129288SN/A# 134486SN/A# Redistribution and use in source and binary forms, with or without 144486SN/A# modification, are permitted provided that the following conditions are 154486SN/A# met: redistributions of source code must retain the above copyright 164486SN/A# notice, this list of conditions and the following disclaimer; 174486SN/A# redistributions in binary form must reproduce the above copyright 184486SN/A# notice, this list of conditions and the following disclaimer in the 194486SN/A# documentation and/or other materials provided with the distribution; 204486SN/A# neither the name of the copyright holders nor the names of its 214486SN/A# contributors may be used to endorse or promote products derived from 224486SN/A# this software without specific prior written permission. 234486SN/A# 244486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 254486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 264486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 274486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 294486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 304486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 324486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 334486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 344486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 354486SN/A# 364486SN/A# Authors: Radhika Jagtap 374486SN/A 384486SN/A# Basic elastic traces replay script that configures a Trace CPU 394486SN/A 4011053Sandreas.hansson@arm.comfrom __future__ import print_function 414486SN/Afrom __future__ import absolute_import 423102SN/A 438833SN/Aimport optparse 442826SN/A 458831SN/Afrom m5.util import addToPath, fatal 4612600Sodanrc@yahoo.com.br 479796SN/AaddToPath('../') 481615SN/A 4912724Snikos.nikoleris@arm.comfrom common import Options 5012724Snikos.nikoleris@arm.comfrom common import Simulation 5112724Snikos.nikoleris@arm.comfrom common import CacheConfig 5212724Snikos.nikoleris@arm.comfrom common import MemConfig 5312724Snikos.nikoleris@arm.comfrom common.Caches import * 5412724Snikos.nikoleris@arm.com 552826SN/Aparser = optparse.OptionParser() 561366SN/AOptions.addCommonOptions(parser) 5711053Sandreas.hansson@arm.com 589338SN/Aif '--ruby' in sys.argv: 5910816SN/A print("This script does not support Ruby configuration, mainly" 6010816SN/A " because Trace CPU has been tested only with classic memory system") 6110816SN/A sys.exit(1) 6210816SN/A 6311722Ssophiane.senni@gmail.com(options, args) = parser.parse_args() 6411722Ssophiane.senni@gmail.com 6510816SN/Aif args: 6610816SN/A print("Error: script doesn't take any positional arguments") 6712513Sodanrc@yahoo.com.br sys.exit(1) 6812513Sodanrc@yahoo.com.br 6912513Sodanrc@yahoo.com.brnumThreads = 1 701310SN/A 7110816SN/Aif options.cpu_type != "TraceCPU": 7210816SN/A fatal("This is a script for elastic trace replay simulation, use "\ 7310816SN/A "--cpu-type=TraceCPU\n"); 7410816SN/A 7510816SN/Aif options.num_cpus > 1: 7610816SN/A fatal("This script does not support multi-processor trace replay.\n") 7710816SN/A 7810884SN/A# In this case FutureClass will be None as there is not fast forwarding or 7910816SN/A# switching 8010816SN/A(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 815875SN/ACPUClass.numThreads = numThreads 8210816SN/A 8310816SN/Asystem = System(cpu = CPUClass(cpu_id=0), 8412600Sodanrc@yahoo.com.br mem_mode = test_mem_mode, 8512600Sodanrc@yahoo.com.br mem_ranges = [AddrRange(options.mem_size)], 8612600Sodanrc@yahoo.com.br cache_line_size = options.cacheline_size) 8712600Sodanrc@yahoo.com.br 8810025SN/A# Create a top-level voltage domain 8910025SN/Asystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 9010816SN/A 9110816SN/A# Create a source clock for the system. This is used as the clock period for 9210816SN/A# xbar and memory 9310816SN/Asystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 9410816SN/A voltage_domain = system.voltage_domain) 9510816SN/A 9610816SN/A# Create a CPU voltage domain 9710816SN/Asystem.cpu_voltage_domain = VoltageDomain() 9811053Sandreas.hansson@arm.com 9912724Snikos.nikoleris@arm.com# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock 10012724Snikos.nikoleris@arm.com# is actually used only by the caches connected to the CPU. 10112724Snikos.nikoleris@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 10212724Snikos.nikoleris@arm.com voltage_domain = 10312724Snikos.nikoleris@arm.com system.cpu_voltage_domain) 10412724Snikos.nikoleris@arm.com 10512724Snikos.nikoleris@arm.com# All cpus belong to a common cpu_clk_domain, therefore running at a common 10611197Sandreas.hansson@arm.com# frequency. 10711197Sandreas.hansson@arm.comfor cpu in system.cpu: 10811197Sandreas.hansson@arm.com cpu.clk_domain = system.cpu_clk_domain 10911197Sandreas.hansson@arm.com 11011197Sandreas.hansson@arm.com# BaseCPU no longer has default values for the BaseCPU.isa 11111197Sandreas.hansson@arm.com# createThreads() is needed to fill in the cpu.isa 11211197Sandreas.hansson@arm.comfor cpu in system.cpu: 11311197Sandreas.hansson@arm.com cpu.createThreads() 11411197Sandreas.hansson@arm.com 11511197Sandreas.hansson@arm.com# Assign input trace files to the Trace CPU 11611197Sandreas.hansson@arm.comsystem.cpu.instTraceFile=options.inst_trace_file 11711197Sandreas.hansson@arm.comsystem.cpu.dataTraceFile=options.data_trace_file 11811199Sandreas.hansson@arm.com 11912724Snikos.nikoleris@arm.com# Configure the classic memory system options 12012724Snikos.nikoleris@arm.comMemClass = Simulation.setMemClass(options) 12112724Snikos.nikoleris@arm.comsystem.membus = SystemXBar() 12212724Snikos.nikoleris@arm.comsystem.system_port = system.membus.slave 12312726Snikos.nikoleris@arm.comCacheConfig.config_cache(options, system) 12412726Snikos.nikoleris@arm.comMemConfig.config_mem(options, system) 12512726Snikos.nikoleris@arm.com 12612726Snikos.nikoleris@arm.comroot = Root(full_system = False, system = system) 12712726Snikos.nikoleris@arm.comSimulation.run(options, root, system, FutureClass) 12812726Snikos.nikoleris@arm.com