fs_bigLITTLE.py revision 14032
1# Copyright (c) 2016-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Gabor Dozsa 37# Andreas Sandberg 38 39# This is an example configuration script for full system simulation of 40# a generic ARM bigLITTLE system. 41 42 43from __future__ import print_function 44from __future__ import absolute_import 45 46import argparse 47import os 48import sys 49import m5 50import m5.util 51from m5.objects import * 52 53m5.util.addToPath("../../") 54 55from common import SysPaths 56from common import CpuConfig 57from common.cores.arm import ex5_big, ex5_LITTLE 58 59import devices 60from devices import AtomicCluster, KvmCluster 61 62 63default_kernel = 'vmlinux4.3.aarch64' 64default_disk = 'aarch64-ubuntu-trusty-headless.img' 65default_rcs = 'bootscript.rcS' 66 67default_mem_size= "2GB" 68 69def _to_ticks(value): 70 """Helper function to convert a latency from string format to Ticks""" 71 72 return m5.ticks.fromSeconds(m5.util.convert.anyToLatency(value)) 73 74def _using_pdes(root): 75 """Determine if the simulator is using multiple parallel event queues""" 76 77 for obj in root.descendants(): 78 if not m5.proxy.isproxy(obj.eventq_index) and \ 79 obj.eventq_index != root.eventq_index: 80 return True 81 82 return False 83 84 85class BigCluster(devices.CpuCluster): 86 def __init__(self, system, num_cpus, cpu_clock, 87 cpu_voltage="1.0V"): 88 cpu_config = [ CpuConfig.get("O3_ARM_v7a_3"), devices.L1I, devices.L1D, 89 devices.WalkCache, devices.L2 ] 90 super(BigCluster, self).__init__(system, num_cpus, cpu_clock, 91 cpu_voltage, *cpu_config) 92 93class LittleCluster(devices.CpuCluster): 94 def __init__(self, system, num_cpus, cpu_clock, 95 cpu_voltage="1.0V"): 96 cpu_config = [ CpuConfig.get("MinorCPU"), devices.L1I, devices.L1D, 97 devices.WalkCache, devices.L2 ] 98 super(LittleCluster, self).__init__(system, num_cpus, cpu_clock, 99 cpu_voltage, *cpu_config) 100 101class Ex5BigCluster(devices.CpuCluster): 102 def __init__(self, system, num_cpus, cpu_clock, 103 cpu_voltage="1.0V"): 104 cpu_config = [ CpuConfig.get("ex5_big"), ex5_big.L1I, ex5_big.L1D, 105 ex5_big.WalkCache, ex5_big.L2 ] 106 super(Ex5BigCluster, self).__init__(system, num_cpus, cpu_clock, 107 cpu_voltage, *cpu_config) 108 109class Ex5LittleCluster(devices.CpuCluster): 110 def __init__(self, system, num_cpus, cpu_clock, 111 cpu_voltage="1.0V"): 112 cpu_config = [ CpuConfig.get("ex5_LITTLE"), ex5_LITTLE.L1I, 113 ex5_LITTLE.L1D, ex5_LITTLE.WalkCache, ex5_LITTLE.L2 ] 114 super(Ex5LittleCluster, self).__init__(system, num_cpus, cpu_clock, 115 cpu_voltage, *cpu_config) 116 117def createSystem(caches, kernel, bootscript, disks=[]): 118 sys = devices.SimpleSystem(caches, default_mem_size, 119 kernel=SysPaths.binary(kernel), 120 readfile=bootscript) 121 122 sys.mem_ctrls = [ SimpleMemory(range=r, port=sys.membus.master) 123 for r in sys.mem_ranges ] 124 125 sys.connect() 126 127 # Attach disk images 128 if disks: 129 def cow_disk(image_file): 130 image = CowDiskImage() 131 image.child.image_file = SysPaths.disk(image_file) 132 return image 133 134 sys.disk_images = [ cow_disk(f) for f in disks ] 135 sys.pci_vio_block = [ PciVirtIO(vio=VirtIOBlock(image=img)) 136 for img in sys.disk_images ] 137 for dev in sys.pci_vio_block: 138 sys.attach_pci(dev) 139 140 sys.realview.setupBootLoader(sys.membus, sys, SysPaths.binary) 141 142 return sys 143 144cpu_types = { 145 "atomic" : (AtomicCluster, AtomicCluster), 146 "timing" : (BigCluster, LittleCluster), 147 "exynos" : (Ex5BigCluster, Ex5LittleCluster), 148} 149 150# Only add the KVM CPU if it has been compiled into gem5 151if devices.have_kvm: 152 cpu_types["kvm"] = (KvmCluster, KvmCluster) 153 154 155def addOptions(parser): 156 parser.add_argument("--restore-from", type=str, default=None, 157 help="Restore from checkpoint") 158 parser.add_argument("--dtb", type=str, default=None, 159 help="DTB file to load") 160 parser.add_argument("--kernel", type=str, default=default_kernel, 161 help="Linux kernel") 162 parser.add_argument("--disk", action="append", type=str, default=[], 163 help="Disks to instantiate") 164 parser.add_argument("--bootscript", type=str, default=default_rcs, 165 help="Linux bootscript") 166 parser.add_argument("--cpu-type", type=str, choices=cpu_types.keys(), 167 default="timing", 168 help="CPU simulation mode. Default: %(default)s") 169 parser.add_argument("--kernel-init", type=str, default="/sbin/init", 170 help="Override init") 171 parser.add_argument("--big-cpus", type=int, default=1, 172 help="Number of big CPUs to instantiate") 173 parser.add_argument("--little-cpus", type=int, default=1, 174 help="Number of little CPUs to instantiate") 175 parser.add_argument("--caches", action="store_true", default=False, 176 help="Instantiate caches") 177 parser.add_argument("--last-cache-level", type=int, default=2, 178 help="Last level of caches (e.g. 3 for L3)") 179 parser.add_argument("--big-cpu-clock", type=str, default="2GHz", 180 help="Big CPU clock frequency") 181 parser.add_argument("--little-cpu-clock", type=str, default="1GHz", 182 help="Little CPU clock frequency") 183 parser.add_argument("--sim-quantum", type=str, default="1ms", 184 help="Simulation quantum for parallel simulation. " \ 185 "Default: %(default)s") 186 parser.add_argument("-P", "--param", action="append", default=[], 187 help="Set a SimObject parameter relative to the root node. " 188 "An extended Python multi range slicing syntax can be used " 189 "for arrays. For example: " 190 "'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' " 191 "sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 " 192 "Direct parameters of the root object are not accessible, " 193 "only parameters of its children.") 194 return parser 195 196def build(options): 197 m5.ticks.fixGlobalFrequency() 198 199 kernel_cmd = [ 200 "earlyprintk=pl011,0x1c090000", 201 "console=ttyAMA0", 202 "lpj=19988480", 203 "norandmaps", 204 "loglevel=8", 205 "mem=%s" % default_mem_size, 206 "root=/dev/vda1", 207 "rw", 208 "init=%s" % options.kernel_init, 209 "vmalloc=768MB", 210 ] 211 212 root = Root(full_system=True) 213 214 disks = [default_disk] if len(options.disk) == 0 else options.disk 215 system = createSystem(options.caches, 216 options.kernel, 217 options.bootscript, 218 disks=disks) 219 220 root.system = system 221 system.boot_osflags = " ".join(kernel_cmd) 222 223 if options.big_cpus + options.little_cpus == 0: 224 m5.util.panic("Empty CPU clusters") 225 226 big_model, little_model = cpu_types[options.cpu_type] 227 228 all_cpus = [] 229 # big cluster 230 if options.big_cpus > 0: 231 system.bigCluster = big_model(system, options.big_cpus, 232 options.big_cpu_clock) 233 system.mem_mode = system.bigCluster.memoryMode() 234 all_cpus += system.bigCluster.cpus 235 236 # little cluster 237 if options.little_cpus > 0: 238 system.littleCluster = little_model(system, options.little_cpus, 239 options.little_cpu_clock) 240 system.mem_mode = system.littleCluster.memoryMode() 241 all_cpus += system.littleCluster.cpus 242 243 # Figure out the memory mode 244 if options.big_cpus > 0 and options.little_cpus > 0 and \ 245 system.bigCluster.memoryMode() != system.littleCluster.memoryMode(): 246 m5.util.panic("Memory mode missmatch among CPU clusters") 247 248 249 # create caches 250 system.addCaches(options.caches, options.last_cache_level) 251 if not options.caches: 252 if options.big_cpus > 0 and system.bigCluster.requireCaches(): 253 m5.util.panic("Big CPU model requires caches") 254 if options.little_cpus > 0 and system.littleCluster.requireCaches(): 255 m5.util.panic("Little CPU model requires caches") 256 257 # Create a KVM VM and do KVM-specific configuration 258 if issubclass(big_model, KvmCluster): 259 _build_kvm(system, all_cpus) 260 261 # Linux device tree 262 if options.dtb is not None: 263 system.dtb_filename = SysPaths.binary(options.dtb) 264 else: 265 system.generateDtb(m5.options.outdir, 'system.dtb') 266 267 return root 268 269def _build_kvm(system, cpus): 270 system.kvm_vm = KvmVM() 271 272 # Assign KVM CPUs to their own event queues / threads. This 273 # has to be done after creating caches and other child objects 274 # since these mustn't inherit the CPU event queue. 275 if len(cpus) > 1: 276 device_eq = 0 277 first_cpu_eq = 1 278 for idx, cpu in enumerate(cpus): 279 # Child objects usually inherit the parent's event 280 # queue. Override that and use the same event queue for 281 # all devices. 282 for obj in cpu.descendants(): 283 obj.eventq_index = device_eq 284 cpu.eventq_index = first_cpu_eq + idx 285 286 287 288def instantiate(options, checkpoint_dir=None): 289 # Setup the simulation quantum if we are running in PDES-mode 290 # (e.g., when using KVM) 291 root = Root.getInstance() 292 if root and _using_pdes(root): 293 m5.util.inform("Running in PDES mode with a %s simulation quantum.", 294 options.sim_quantum) 295 root.sim_quantum = _to_ticks(options.sim_quantum) 296 297 # Get and load from the chkpt or simpoint checkpoint 298 if options.restore_from: 299 if checkpoint_dir and not os.path.isabs(options.restore_from): 300 cpt = os.path.join(checkpoint_dir, options.restore_from) 301 else: 302 cpt = options.restore_from 303 304 m5.util.inform("Restoring from checkpoint %s", cpt) 305 m5.instantiate(cpt) 306 else: 307 m5.instantiate() 308 309 310def run(checkpoint_dir=m5.options.outdir): 311 # start simulation (and drop checkpoints when requested) 312 while True: 313 event = m5.simulate() 314 exit_msg = event.getCause() 315 if exit_msg == "checkpoint": 316 print("Dropping checkpoint at tick %d" % m5.curTick()) 317 cpt_dir = os.path.join(checkpoint_dir, "cpt.%d" % m5.curTick()) 318 m5.checkpoint(cpt_dir) 319 print("Checkpoint done.") 320 else: 321 print(exit_msg, " @ ", m5.curTick()) 322 break 323 324 sys.exit(event.getCode()) 325 326 327def main(): 328 parser = argparse.ArgumentParser( 329 description="Generic ARM big.LITTLE configuration") 330 addOptions(parser) 331 options = parser.parse_args() 332 root = build(options) 333 root.apply_config(options.param) 334 instantiate(options) 335 run() 336 337 338if __name__ == "__m5_main__": 339 main() 340