fs_bigLITTLE.py revision 11630:6e2408ad4425
12810Srdreslin@umich.edu# Copyright (c) 2016 ARM Limited 29796Sprakash.ramrakhyani@arm.com# All rights reserved. 39347SAndreas.Sandberg@arm.com# 49347SAndreas.Sandberg@arm.com# The license below extends only to copyright in the software and shall 59347SAndreas.Sandberg@arm.com# not be construed as granting a license to any other intellectual 69347SAndreas.Sandberg@arm.com# property including but not limited to intellectual property relating 79347SAndreas.Sandberg@arm.com# to a hardware implementation of the functionality of the software 89347SAndreas.Sandberg@arm.com# licensed hereunder. You may use the software subject to the license 99347SAndreas.Sandberg@arm.com# terms below provided that you ensure that this notice is replicated 109347SAndreas.Sandberg@arm.com# unmodified and in its entirety in all distributions of the software, 119347SAndreas.Sandberg@arm.com# modified or unmodified, in source code or in binary form. 129347SAndreas.Sandberg@arm.com# 139347SAndreas.Sandberg@arm.com# Redistribution and use in source and binary forms, with or without 142810Srdreslin@umich.edu# modification, are permitted provided that the following conditions are 152810Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright 162810Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer; 172810Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright 182810Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the 192810Srdreslin@umich.edu# documentation and/or other materials provided with the distribution; 202810Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its 212810Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from 222810Srdreslin@umich.edu# this software without specific prior written permission. 232810Srdreslin@umich.edu# 242810Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 252810Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 262810Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272810Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282810Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292810Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 302810Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 312810Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 322810Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 332810Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 342810Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 352810Srdreslin@umich.edu# 362810Srdreslin@umich.edu# Authors: Gabor Dozsa 372810Srdreslin@umich.edu# Andreas Sandberg 382810Srdreslin@umich.edu 392810Srdreslin@umich.edu# This is an example configuration script for full system simulation of 402810Srdreslin@umich.edu# a generic ARM bigLITTLE system. 412810Srdreslin@umich.edu 422810Srdreslin@umich.edu 432810Srdreslin@umich.eduimport argparse 442810Srdreslin@umich.eduimport os 452810Srdreslin@umich.eduimport sys 462810Srdreslin@umich.eduimport m5 472810Srdreslin@umich.edufrom m5.objects import * 486216Snate@binkert.org 496216Snate@binkert.orgm5.util.addToPath("../../common") 502810Srdreslin@umich.eduimport SysPaths 512810Srdreslin@umich.eduimport CpuConfig 5211168Sandreas.hansson@arm.com 532810Srdreslin@umich.eduimport devices 548229Snate@binkert.org 555338Sstever@gmail.com 562810Srdreslin@umich.edudefault_dtb = 'armv8_gem5_v1_big_little_2_2.dtb' 579796Sprakash.ramrakhyani@arm.comdefault_kernel = 'vmlinux4.3.aarch64' 582810Srdreslin@umich.edudefault_disk = 'aarch64-ubuntu-trusty-headless.img' 592810Srdreslin@umich.edudefault_rcs = 'bootscript.rcS' 602810Srdreslin@umich.edu 612810Srdreslin@umich.edudefault_mem_size= "2GB" 622810Srdreslin@umich.edu 632810Srdreslin@umich.edu 642810Srdreslin@umich.educlass BigCluster(devices.CpuCluster): 652810Srdreslin@umich.edu def __init__(self, system, num_cpus, cpu_clock, 662810Srdreslin@umich.edu cpu_voltage="1.0V"): 672810Srdreslin@umich.edu cpu_config = [ CpuConfig.get("arm_detailed"), devices.L1I, devices.L1D, 682810Srdreslin@umich.edu devices.WalkCache, devices.L2 ] 692810Srdreslin@umich.edu super(BigCluster, self).__init__(system, num_cpus, cpu_clock, 702810Srdreslin@umich.edu cpu_voltage, *cpu_config) 712810Srdreslin@umich.edu 722810Srdreslin@umich.educlass LittleCluster(devices.CpuCluster): 732810Srdreslin@umich.edu def __init__(self, system, num_cpus, cpu_clock, 742810Srdreslin@umich.edu cpu_voltage="1.0V"): 752810Srdreslin@umich.edu cpu_config = [ CpuConfig.get("minor"), devices.L1I, devices.L1D, 762810Srdreslin@umich.edu devices.WalkCache, devices.L2 ] 772810Srdreslin@umich.edu super(LittleCluster, self).__init__(system, num_cpus, cpu_clock, 782810Srdreslin@umich.edu cpu_voltage, *cpu_config) 792810Srdreslin@umich.edu 802810Srdreslin@umich.edu 812810Srdreslin@umich.edudef createSystem(kernel, bootscript, disks=[]): 822810Srdreslin@umich.edu sys = devices.SimpleSystem(kernel=SysPaths.binary(kernel), 832810Srdreslin@umich.edu readfile=bootscript, 842810Srdreslin@umich.edu machine_type="DTOnly") 852810Srdreslin@umich.edu 862810Srdreslin@umich.edu mem_region = sys.realview._mem_regions[0] 872810Srdreslin@umich.edu sys.mem_ctrls = SimpleMemory( 882810Srdreslin@umich.edu range=AddrRange(start=mem_region[0], size=default_mem_size)) 892810Srdreslin@umich.edu sys.mem_ctrls.port = sys.membus.master 902810Srdreslin@umich.edu 912810Srdreslin@umich.edu sys.connect() 922810Srdreslin@umich.edu 932810Srdreslin@umich.edu # Attach disk images 946227Snate@binkert.org if disks: 952810Srdreslin@umich.edu def cow_disk(image_file): 962810Srdreslin@umich.edu image = CowDiskImage() 972810Srdreslin@umich.edu image.child.image_file = SysPaths.disk(image_file) 982810Srdreslin@umich.edu return image 992810Srdreslin@umich.edu 1002810Srdreslin@umich.edu sys.disk_images = [ cow_disk(f) for f in disks ] 1016227Snate@binkert.org sys.pci_vio_block = [ PciVirtIO(vio=VirtIOBlock(image=img)) 1022810Srdreslin@umich.edu for img in sys.disk_images ] 1032810Srdreslin@umich.edu for dev in sys.pci_vio_block: 1042810Srdreslin@umich.edu sys.attach_pci(dev) 1052810Srdreslin@umich.edu 1062810Srdreslin@umich.edu sys.realview.setupBootLoader(sys.membus, sys, SysPaths.binary) 1072810Srdreslin@umich.edu 1082810Srdreslin@umich.edu return sys 1092810Srdreslin@umich.edu 1102810Srdreslin@umich.edu 1112810Srdreslin@umich.edudef main(): 11211168Sandreas.hansson@arm.com parser = argparse.ArgumentParser( 1132810Srdreslin@umich.edu description="Generic ARM big.LITTLE configuration") 1142810Srdreslin@umich.edu 1152810Srdreslin@umich.edu parser.add_argument("--restore-from", type=str, default=None, 1162810Srdreslin@umich.edu help="Restore from checkpoint") 1172810Srdreslin@umich.edu parser.add_argument("--dtb", type=str, default=default_dtb, 1182810Srdreslin@umich.edu help="DTB file to load") 1192810Srdreslin@umich.edu parser.add_argument("--kernel", type=str, default=default_kernel, 1202810Srdreslin@umich.edu help="Linux kernel") 1212810Srdreslin@umich.edu parser.add_argument("--disk", action="append", type=str, default=[], 1222810Srdreslin@umich.edu help="Disks to instantiate") 1232810Srdreslin@umich.edu parser.add_argument("--bootscript", type=str, default=default_rcs, 1242810Srdreslin@umich.edu help="Linux bootscript") 1252810Srdreslin@umich.edu parser.add_argument("--atomic", action="store_true", default=False, 1262810Srdreslin@umich.edu help="Use atomic CPUs") 1272810Srdreslin@umich.edu parser.add_argument("--kernel-init", type=str, default="/sbin/init", 1282810Srdreslin@umich.edu help="Override init") 1292810Srdreslin@umich.edu parser.add_argument("--big-cpus", type=int, default=1, 1302810Srdreslin@umich.edu help="Number of big CPUs to instantiate") 1312810Srdreslin@umich.edu parser.add_argument("--little-cpus", type=int, default=1, 1322810Srdreslin@umich.edu help="Number of little CPUs to instantiate") 1332810Srdreslin@umich.edu parser.add_argument("--caches", action="store_true", default=False, 1342810Srdreslin@umich.edu help="Instantiate caches") 1352810Srdreslin@umich.edu parser.add_argument("--last-cache-level", type=int, default=2, 1362810Srdreslin@umich.edu help="Last level of caches (e.g. 3 for L3)") 1372810Srdreslin@umich.edu parser.add_argument("--big-cpu-clock", type=str, default="2GHz", 1382810Srdreslin@umich.edu help="Big CPU clock frequency") 1392810Srdreslin@umich.edu parser.add_argument("--little-cpu-clock", type=str, default="1GHz", 1402810Srdreslin@umich.edu help="Little CPU clock frequency") 1412810Srdreslin@umich.edu 1422810Srdreslin@umich.edu m5.ticks.fixGlobalFrequency() 1432810Srdreslin@umich.edu 1442810Srdreslin@umich.edu options = parser.parse_args() 1452810Srdreslin@umich.edu 1462810Srdreslin@umich.edu kernel_cmd = [ 1475999Snate@binkert.org "earlyprintk=pl011,0x1c090000", 1482810Srdreslin@umich.edu "console=ttyAMA0", 1495999Snate@binkert.org "lpj=19988480", 1502810Srdreslin@umich.edu "norandmaps", 1515999Snate@binkert.org "loglevel=8", 1522810Srdreslin@umich.edu "mem=%s" % default_mem_size, 1532810Srdreslin@umich.edu "root=/dev/vda1", 1542810Srdreslin@umich.edu "rw", 1552810Srdreslin@umich.edu "init=%s" % options.kernel_init, 1562810Srdreslin@umich.edu "vmalloc=768MB", 1572810Srdreslin@umich.edu ] 1589796Sprakash.ramrakhyani@arm.com 1599796Sprakash.ramrakhyani@arm.com root = Root(full_system=True) 1609796Sprakash.ramrakhyani@arm.com 1612810Srdreslin@umich.edu disks = default_disk if len(options.disk) == 0 else options.disk 1622810Srdreslin@umich.edu system = createSystem(options.kernel, options.bootscript, disks=disks) 1632810Srdreslin@umich.edu 1649796Sprakash.ramrakhyani@arm.com root.system = system 1659086Sandreas.hansson@arm.com system.boot_osflags = " ".join(kernel_cmd) 1662810Srdreslin@umich.edu 1672810Srdreslin@umich.edu AtomicCluster = devices.AtomicCluster 1682810Srdreslin@umich.edu 1692810Srdreslin@umich.edu if options.big_cpus + options.little_cpus == 0: 1702810Srdreslin@umich.edu m5.util.panic("Empty CPU clusters") 1719796Sprakash.ramrakhyani@arm.com 1722810Srdreslin@umich.edu # big cluster 1732810Srdreslin@umich.edu if options.big_cpus > 0: 1743862Sstever@eecs.umich.edu if options.atomic: 1753862Sstever@eecs.umich.edu system.bigCluster = AtomicCluster(system, options.big_cpus, 1762810Srdreslin@umich.edu options.big_cpu_clock) 17710815Sdavid.guillen@arm.com else: 1782810Srdreslin@umich.edu system.bigCluster = BigCluster(system, options.big_cpus, 1792810Srdreslin@umich.edu options.big_cpu_clock) 1805716Shsul@eecs.umich.edu mem_mode = system.bigCluster.memoryMode() 1815716Shsul@eecs.umich.edu # little cluster 1825716Shsul@eecs.umich.edu if options.little_cpus > 0: 1835716Shsul@eecs.umich.edu if options.atomic: 1842810Srdreslin@umich.edu system.littleCluster = AtomicCluster(system, options.little_cpus, 18510028SGiacomo.Gabrielli@arm.com options.little_cpu_clock) 1862810Srdreslin@umich.edu 1872810Srdreslin@umich.edu else: 1882810Srdreslin@umich.edu system.littleCluster = LittleCluster(system, options.little_cpus, 1892810Srdreslin@umich.edu options.little_cpu_clock) 1902810Srdreslin@umich.edu mem_mode = system.littleCluster.memoryMode() 19110815Sdavid.guillen@arm.com 19210815Sdavid.guillen@arm.com if options.big_cpus > 0 and options.little_cpus > 0: 19310815Sdavid.guillen@arm.com if system.bigCluster.memoryMode() != system.littleCluster.memoryMode(): 19410815Sdavid.guillen@arm.com m5.util.panic("Memory mode missmatch among CPU clusters") 19510815Sdavid.guillen@arm.com system.mem_mode = mem_mode 19610815Sdavid.guillen@arm.com 19710815Sdavid.guillen@arm.com # create caches 19810815Sdavid.guillen@arm.com system.addCaches(options.caches, options.last_cache_level) 1992810Srdreslin@umich.edu if not options.caches: 2002810Srdreslin@umich.edu if options.big_cpus > 0 and system.bigCluster.requireCaches(): 2012810Srdreslin@umich.edu m5.util.panic("Big CPU model requires caches") 2022810Srdreslin@umich.edu if options.little_cpus > 0 and system.littleCluster.requireCaches(): 20310028SGiacomo.Gabrielli@arm.com m5.util.panic("Little CPU model requires caches") 2042810Srdreslin@umich.edu 2052810Srdreslin@umich.edu # Linux device tree 2062810Srdreslin@umich.edu system.dtb_filename = SysPaths.binary(options.dtb) 20710815Sdavid.guillen@arm.com 2082810Srdreslin@umich.edu # Get and load from the chkpt or simpoint checkpoint 2092810Srdreslin@umich.edu if options.restore_from is not None: 2102810Srdreslin@umich.edu m5.instantiate(options.restore_from) 2112982Sstever@eecs.umich.edu else: 2122810Srdreslin@umich.edu m5.instantiate() 2132810Srdreslin@umich.edu 21410815Sdavid.guillen@arm.com # start simulation (and drop checkpoints when requested) 2155717Shsul@eecs.umich.edu while True: 21610815Sdavid.guillen@arm.com event = m5.simulate() 2172810Srdreslin@umich.edu exit_msg = event.getCause() 2182810Srdreslin@umich.edu if exit_msg == "checkpoint": 2192810Srdreslin@umich.edu print "Dropping checkpoint at tick %d" % m5.curTick() 2202810Srdreslin@umich.edu cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick()) 2212810Srdreslin@umich.edu m5.checkpoint(os.path.join(cpt_dir)) 2226227Snate@binkert.org print "Checkpoint done." 2236227Snate@binkert.org else: 2242810Srdreslin@umich.edu print exit_msg, " @ ", m5.curTick() 2252810Srdreslin@umich.edu break 2262810Srdreslin@umich.edu 2272810Srdreslin@umich.edu sys.exit(event.getCode()) 2282810Srdreslin@umich.edu 2292810Srdreslin@umich.edu 2302810Srdreslin@umich.eduif __name__ == "__m5_main__": 2312810Srdreslin@umich.edu main() 2326227Snate@binkert.org