fs_bigLITTLE.py revision 11569:2eae1dfaa791 
1# Copyright (c) 2016 ARM Limited
2# All rights reserved.
3#
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35#
36# Authors: Gabor Dozsa
37#          Andreas Sandberg
38
39# This is an example configuration script for full system simulation of
40# a generic ARM bigLITTLE system.
41
42
43import argparse
44import os
45import sys
46import m5
47from m5.objects import *
48
49m5.util.addToPath("../../common")
50import SysPaths
51import CpuConfig
52
53import devices
54
55
56default_dtb = 'armv8_gem5_v1_big_little_2_2.dtb'
57default_kernel = 'vmlinux4.3.aarch64'
58default_disk = 'aarch64-ubuntu-trusty-headless.img'
59default_rcs = 'bootscript.rcS'
60
61default_mem_size= "2GB"
62
63def createSystem(kernel, mem_mode, bootscript, disks=[]):
64    sys = devices.SimpleSystem(kernel=SysPaths.binary(kernel),
65                               readfile=bootscript,
66                               mem_mode=mem_mode,
67                               machine_type="DTOnly")
68
69    mem_region = sys.realview._mem_regions[0]
70    sys.mem_ctrls = SimpleMemory(
71        range=AddrRange(start=mem_region[0], size=default_mem_size))
72    sys.mem_ctrls.port = sys.membus.master
73
74    sys.connect()
75
76    # Attach disk images
77    if disks:
78        def cow_disk(image_file):
79            image = CowDiskImage()
80            image.child.image_file = SysPaths.disk(image_file)
81            return image
82
83        sys.disk_images = [ cow_disk(f) for f in disks ]
84        sys.pci_vio_block = [ PciVirtIO(vio=VirtIOBlock(image=img))
85                              for img in sys.disk_images ]
86        for dev in sys.pci_vio_block:
87            sys.attach_pci(dev)
88
89    sys.realview.setupBootLoader(sys.membus, sys, SysPaths.binary)
90
91    return sys
92
93
94class CpuCluster(SubSystem):
95    def addCPUs(self, cpu_config, num_cpus, cpu_clock, cpu_voltage="1.0V"):
96        try:
97            self._cluster_id
98            m5.util.panic("CpuCluster.addCPUs() must be called exactly once")
99        except AttributeError:
100            pass
101
102        assert num_cpus > 0
103        system = self._parent
104        self._cluster_id = len(system._clusters)
105        system._clusters.append(self)
106        self._config = cpu_config
107
108        self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
109        self.clk_domain = SrcClockDomain(clock=cpu_clock,
110                                         voltage_domain=self.voltage_domain)
111
112        cpu_class = cpu_config['cpu']
113        self.cpus = [ cpu_class(cpu_id=len(system._cpus) + idx,
114                                clk_domain=self.clk_domain)
115                      for idx in range(num_cpus) ]
116
117        for cpu in self.cpus:
118            cpu.createThreads()
119            cpu.createInterruptController()
120            cpu.socket_id = self._cluster_id
121            system._cpus.append(cpu)
122
123    def createCache(self, key):
124        try:
125            return self._config[key]()
126        except KeyError:
127            return None
128
129    def addL1(self):
130        self._cluster_id
131        for cpu in self.cpus:
132            l1i = self.createCache('l1i')
133            l1d = self.createCache('l1d')
134            iwc = self.createCache('wcache')
135            dwc = self.createCache('wcache')
136            cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
137
138    def addL2(self, clk_domain):
139        self._cluster_id
140        self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
141        #self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain,
142        #snoop_filter=NULL)
143        self.l2 = self._config['l2']()
144        for cpu in self.cpus:
145            cpu.connectAllPorts(self.toL2Bus)
146        self.toL2Bus.master = self.l2.cpu_side
147
148    def connectMemSide(self, bus):
149        self._cluster_id
150        bus.slave
151        try:
152            self.l2.mem_side = bus.slave
153        except AttributeError:
154            for cpu in self.cpus:
155                cpu.connectAllPorts(bus)
156
157
158def addCaches(system, last_cache_level):
159    cluster_mem_bus = system.membus
160    assert last_cache_level >= 1 and last_cache_level <= 3
161    for cluster in system._clusters:
162        cluster.addL1()
163    if last_cache_level > 1:
164        for cluster in system._clusters:
165            cluster.addL2(cluster.clk_domain)
166    if last_cache_level > 2:
167        max_clock_cluster = max(system._clusters,
168                                key=lambda c: c.clk_domain.clock[0])
169        system.l3 = devices.L3(clk_domain=max_clock_cluster.clk_domain)
170        system.toL3Bus = L2XBar(width=64)
171        system.toL3Bus.master = system.l3.cpu_side
172        system.l3.mem_side = system.membus.slave
173        cluster_mem_bus = system.toL3Bus
174
175    return cluster_mem_bus
176
177
178def main():
179    parser = argparse.ArgumentParser(
180        description="Generic ARM big.LITTLE configuration")
181
182    parser.add_argument("--restore-from", type=str, default=None,
183                        help="Restore from checkpoint")
184    parser.add_argument("--dtb", type=str, default=default_dtb,
185                        help="DTB file to load")
186    parser.add_argument("--kernel", type=str, default=default_kernel,
187                        help="Linux kernel")
188    parser.add_argument("--disk", action="append", type=str, default=[],
189                        help="Disks to instantiate")
190    parser.add_argument("--bootscript", type=str, default=default_rcs,
191                        help="Linux bootscript")
192    parser.add_argument("--atomic", action="store_true", default=False,
193                        help="Use atomic CPUs")
194    parser.add_argument("--kernel-init", type=str, default="/sbin/init",
195                        help="Override init")
196    parser.add_argument("--big-cpus", type=int, default=1,
197                        help="Number of big CPUs to instantiate")
198    parser.add_argument("--little-cpus", type=int, default=1,
199                        help="Number of little CPUs to instantiate")
200    parser.add_argument("--caches", action="store_true", default=False,
201                        help="Instantiate caches")
202    parser.add_argument("--last-cache-level", type=int, default=2,
203                        help="Last level of caches (e.g. 3 for L3)")
204    parser.add_argument("--big-cpu-clock", type=str, default="2GHz",
205                        help="Big CPU clock frequency")
206    parser.add_argument("--little-cpu-clock", type=str, default="1GHz",
207                        help="Little CPU clock frequency")
208
209    m5.ticks.fixGlobalFrequency()
210
211    options = parser.parse_args()
212
213    if options.atomic:
214        cpu_config = { 'cpu' : AtomicSimpleCPU }
215        big_cpu_config, little_cpu_config = cpu_config, cpu_config
216    else:
217        big_cpu_config = { 'cpu' : CpuConfig.get("arm_detailed"),
218                           'l1i' : devices.L1I,
219                           'l1d' : devices.L1D,
220                           'wcache' : devices.WalkCache,
221                           'l2' : devices.L2 }
222        little_cpu_config = { 'cpu' : MinorCPU,
223                              'l1i' : devices.L1I,
224                              'l1d' : devices.L1D,
225                              'wcache' : devices.WalkCache,
226                              'l2' : devices.L2 }
227
228    big_cpu_class = big_cpu_config['cpu']
229    little_cpu_class = little_cpu_config['cpu']
230
231    kernel_cmd = [
232        "earlyprintk=pl011,0x1c090000",
233        "console=ttyAMA0",
234        "lpj=19988480",
235        "norandmaps",
236        "loglevel=8",
237        "mem=%s" % default_mem_size,
238        "root=/dev/vda1",
239        "rw",
240        "init=%s" % options.kernel_init,
241        "vmalloc=768MB",
242    ]
243
244    root = Root(full_system=True)
245
246    assert big_cpu_class.memory_mode() == little_cpu_class.memory_mode()
247    disks = default_disk if len(options.disk) == 0 else options.disk
248    system = createSystem(options.kernel, big_cpu_class.memory_mode(),
249                          options.bootscript, disks=disks)
250
251    root.system = system
252    system.boot_osflags = " ".join(kernel_cmd)
253
254    # big cluster
255    if options.big_cpus > 0:
256        system.bigCluster = CpuCluster()
257        system.bigCluster.addCPUs(big_cpu_config, options.big_cpus,
258                                  options.big_cpu_clock)
259
260
261    # LITTLE cluster
262    if options.little_cpus > 0:
263        system.littleCluster = CpuCluster()
264        system.littleCluster.addCPUs(little_cpu_config, options.little_cpus,
265                                     options.little_cpu_clock)
266
267    # add caches
268    if options.caches:
269        cluster_mem_bus = addCaches(system, options.last_cache_level)
270    else:
271        if big_cpu_class.require_caches():
272            m5.util.panic("CPU model %s requires caches" % str(big_cpu_class))
273        if little_cpu_class.require_caches():
274            m5.util.panic("CPU model %s requires caches" %
275                          str(little_cpu_class))
276        cluster_mem_bus = system.membus
277
278    # connect each cluster to the memory hierarchy
279    for cluster in system._clusters:
280        cluster.connectMemSide(cluster_mem_bus)
281
282    # Linux device tree
283    system.dtb_filename = SysPaths.binary(options.dtb)
284
285    # Get and load from the chkpt or simpoint checkpoint
286    if options.restore_from is not None:
287        m5.instantiate(options.restore_from)
288    else:
289        m5.instantiate()
290
291    # start simulation (and drop checkpoints when requested)
292    while True:
293        event = m5.simulate()
294        exit_msg = event.getCause()
295        if exit_msg == "checkpoint":
296            print "Dropping checkpoint at tick %d" % m5.curTick()
297            cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick())
298            m5.checkpoint(os.path.join(cpt_dir))
299            print "Checkpoint done."
300        else:
301            print exit_msg, " @ ", m5.curTick()
302            break
303
304    sys.exit(event.getCode())
305
306
307if __name__ == "__m5_main__":
308    main()
309