fs_bigLITTLE.py revision 11569
111569Sgabor.dozsa@arm.com# Copyright (c) 2016 ARM Limited 211569Sgabor.dozsa@arm.com# All rights reserved. 311569Sgabor.dozsa@arm.com# 411569Sgabor.dozsa@arm.com# The license below extends only to copyright in the software and shall 511569Sgabor.dozsa@arm.com# not be construed as granting a license to any other intellectual 611569Sgabor.dozsa@arm.com# property including but not limited to intellectual property relating 711569Sgabor.dozsa@arm.com# to a hardware implementation of the functionality of the software 811569Sgabor.dozsa@arm.com# licensed hereunder. You may use the software subject to the license 911569Sgabor.dozsa@arm.com# terms below provided that you ensure that this notice is replicated 1011569Sgabor.dozsa@arm.com# unmodified and in its entirety in all distributions of the software, 1111569Sgabor.dozsa@arm.com# modified or unmodified, in source code or in binary form. 1211569Sgabor.dozsa@arm.com# 1311569Sgabor.dozsa@arm.com# Redistribution and use in source and binary forms, with or without 1411569Sgabor.dozsa@arm.com# modification, are permitted provided that the following conditions are 1511569Sgabor.dozsa@arm.com# met: redistributions of source code must retain the above copyright 1611569Sgabor.dozsa@arm.com# notice, this list of conditions and the following disclaimer; 1711569Sgabor.dozsa@arm.com# redistributions in binary form must reproduce the above copyright 1811569Sgabor.dozsa@arm.com# notice, this list of conditions and the following disclaimer in the 1911569Sgabor.dozsa@arm.com# documentation and/or other materials provided with the distribution; 2011569Sgabor.dozsa@arm.com# neither the name of the copyright holders nor the names of its 2111569Sgabor.dozsa@arm.com# contributors may be used to endorse or promote products derived from 2211569Sgabor.dozsa@arm.com# this software without specific prior written permission. 2311569Sgabor.dozsa@arm.com# 2411569Sgabor.dozsa@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2511569Sgabor.dozsa@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2611569Sgabor.dozsa@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2711569Sgabor.dozsa@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2811569Sgabor.dozsa@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2911569Sgabor.dozsa@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3011569Sgabor.dozsa@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3111569Sgabor.dozsa@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3211569Sgabor.dozsa@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3311569Sgabor.dozsa@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3411569Sgabor.dozsa@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3511569Sgabor.dozsa@arm.com# 3611569Sgabor.dozsa@arm.com# Authors: Gabor Dozsa 3711569Sgabor.dozsa@arm.com# Andreas Sandberg 3811569Sgabor.dozsa@arm.com 3911569Sgabor.dozsa@arm.com# This is an example configuration script for full system simulation of 4011569Sgabor.dozsa@arm.com# a generic ARM bigLITTLE system. 4111569Sgabor.dozsa@arm.com 4211569Sgabor.dozsa@arm.com 4311569Sgabor.dozsa@arm.comimport argparse 4411569Sgabor.dozsa@arm.comimport os 4511569Sgabor.dozsa@arm.comimport sys 4611569Sgabor.dozsa@arm.comimport m5 4711569Sgabor.dozsa@arm.comfrom m5.objects import * 4811569Sgabor.dozsa@arm.com 4911569Sgabor.dozsa@arm.comm5.util.addToPath("../../common") 5011569Sgabor.dozsa@arm.comimport SysPaths 5111569Sgabor.dozsa@arm.comimport CpuConfig 5211569Sgabor.dozsa@arm.com 5311569Sgabor.dozsa@arm.comimport devices 5411569Sgabor.dozsa@arm.com 5511569Sgabor.dozsa@arm.com 5611569Sgabor.dozsa@arm.comdefault_dtb = 'armv8_gem5_v1_big_little_2_2.dtb' 5711569Sgabor.dozsa@arm.comdefault_kernel = 'vmlinux4.3.aarch64' 5811569Sgabor.dozsa@arm.comdefault_disk = 'aarch64-ubuntu-trusty-headless.img' 5911569Sgabor.dozsa@arm.comdefault_rcs = 'bootscript.rcS' 6011569Sgabor.dozsa@arm.com 6111569Sgabor.dozsa@arm.comdefault_mem_size= "2GB" 6211569Sgabor.dozsa@arm.com 6311569Sgabor.dozsa@arm.comdef createSystem(kernel, mem_mode, bootscript, disks=[]): 6411569Sgabor.dozsa@arm.com sys = devices.SimpleSystem(kernel=SysPaths.binary(kernel), 6511569Sgabor.dozsa@arm.com readfile=bootscript, 6611569Sgabor.dozsa@arm.com mem_mode=mem_mode, 6711569Sgabor.dozsa@arm.com machine_type="DTOnly") 6811569Sgabor.dozsa@arm.com 6911569Sgabor.dozsa@arm.com mem_region = sys.realview._mem_regions[0] 7011569Sgabor.dozsa@arm.com sys.mem_ctrls = SimpleMemory( 7111569Sgabor.dozsa@arm.com range=AddrRange(start=mem_region[0], size=default_mem_size)) 7211569Sgabor.dozsa@arm.com sys.mem_ctrls.port = sys.membus.master 7311569Sgabor.dozsa@arm.com 7411569Sgabor.dozsa@arm.com sys.connect() 7511569Sgabor.dozsa@arm.com 7611569Sgabor.dozsa@arm.com # Attach disk images 7711569Sgabor.dozsa@arm.com if disks: 7811569Sgabor.dozsa@arm.com def cow_disk(image_file): 7911569Sgabor.dozsa@arm.com image = CowDiskImage() 8011569Sgabor.dozsa@arm.com image.child.image_file = SysPaths.disk(image_file) 8111569Sgabor.dozsa@arm.com return image 8211569Sgabor.dozsa@arm.com 8311569Sgabor.dozsa@arm.com sys.disk_images = [ cow_disk(f) for f in disks ] 8411569Sgabor.dozsa@arm.com sys.pci_vio_block = [ PciVirtIO(vio=VirtIOBlock(image=img)) 8511569Sgabor.dozsa@arm.com for img in sys.disk_images ] 8611569Sgabor.dozsa@arm.com for dev in sys.pci_vio_block: 8711569Sgabor.dozsa@arm.com sys.attach_pci(dev) 8811569Sgabor.dozsa@arm.com 8911569Sgabor.dozsa@arm.com sys.realview.setupBootLoader(sys.membus, sys, SysPaths.binary) 9011569Sgabor.dozsa@arm.com 9111569Sgabor.dozsa@arm.com return sys 9211569Sgabor.dozsa@arm.com 9311569Sgabor.dozsa@arm.com 9411569Sgabor.dozsa@arm.comclass CpuCluster(SubSystem): 9511569Sgabor.dozsa@arm.com def addCPUs(self, cpu_config, num_cpus, cpu_clock, cpu_voltage="1.0V"): 9611569Sgabor.dozsa@arm.com try: 9711569Sgabor.dozsa@arm.com self._cluster_id 9811569Sgabor.dozsa@arm.com m5.util.panic("CpuCluster.addCPUs() must be called exactly once") 9911569Sgabor.dozsa@arm.com except AttributeError: 10011569Sgabor.dozsa@arm.com pass 10111569Sgabor.dozsa@arm.com 10211569Sgabor.dozsa@arm.com assert num_cpus > 0 10311569Sgabor.dozsa@arm.com system = self._parent 10411569Sgabor.dozsa@arm.com self._cluster_id = len(system._clusters) 10511569Sgabor.dozsa@arm.com system._clusters.append(self) 10611569Sgabor.dozsa@arm.com self._config = cpu_config 10711569Sgabor.dozsa@arm.com 10811569Sgabor.dozsa@arm.com self.voltage_domain = VoltageDomain(voltage=cpu_voltage) 10911569Sgabor.dozsa@arm.com self.clk_domain = SrcClockDomain(clock=cpu_clock, 11011569Sgabor.dozsa@arm.com voltage_domain=self.voltage_domain) 11111569Sgabor.dozsa@arm.com 11211569Sgabor.dozsa@arm.com cpu_class = cpu_config['cpu'] 11311569Sgabor.dozsa@arm.com self.cpus = [ cpu_class(cpu_id=len(system._cpus) + idx, 11411569Sgabor.dozsa@arm.com clk_domain=self.clk_domain) 11511569Sgabor.dozsa@arm.com for idx in range(num_cpus) ] 11611569Sgabor.dozsa@arm.com 11711569Sgabor.dozsa@arm.com for cpu in self.cpus: 11811569Sgabor.dozsa@arm.com cpu.createThreads() 11911569Sgabor.dozsa@arm.com cpu.createInterruptController() 12011569Sgabor.dozsa@arm.com cpu.socket_id = self._cluster_id 12111569Sgabor.dozsa@arm.com system._cpus.append(cpu) 12211569Sgabor.dozsa@arm.com 12311569Sgabor.dozsa@arm.com def createCache(self, key): 12411569Sgabor.dozsa@arm.com try: 12511569Sgabor.dozsa@arm.com return self._config[key]() 12611569Sgabor.dozsa@arm.com except KeyError: 12711569Sgabor.dozsa@arm.com return None 12811569Sgabor.dozsa@arm.com 12911569Sgabor.dozsa@arm.com def addL1(self): 13011569Sgabor.dozsa@arm.com self._cluster_id 13111569Sgabor.dozsa@arm.com for cpu in self.cpus: 13211569Sgabor.dozsa@arm.com l1i = self.createCache('l1i') 13311569Sgabor.dozsa@arm.com l1d = self.createCache('l1d') 13411569Sgabor.dozsa@arm.com iwc = self.createCache('wcache') 13511569Sgabor.dozsa@arm.com dwc = self.createCache('wcache') 13611569Sgabor.dozsa@arm.com cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc) 13711569Sgabor.dozsa@arm.com 13811569Sgabor.dozsa@arm.com def addL2(self, clk_domain): 13911569Sgabor.dozsa@arm.com self._cluster_id 14011569Sgabor.dozsa@arm.com self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain) 14111569Sgabor.dozsa@arm.com #self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain, 14211569Sgabor.dozsa@arm.com #snoop_filter=NULL) 14311569Sgabor.dozsa@arm.com self.l2 = self._config['l2']() 14411569Sgabor.dozsa@arm.com for cpu in self.cpus: 14511569Sgabor.dozsa@arm.com cpu.connectAllPorts(self.toL2Bus) 14611569Sgabor.dozsa@arm.com self.toL2Bus.master = self.l2.cpu_side 14711569Sgabor.dozsa@arm.com 14811569Sgabor.dozsa@arm.com def connectMemSide(self, bus): 14911569Sgabor.dozsa@arm.com self._cluster_id 15011569Sgabor.dozsa@arm.com bus.slave 15111569Sgabor.dozsa@arm.com try: 15211569Sgabor.dozsa@arm.com self.l2.mem_side = bus.slave 15311569Sgabor.dozsa@arm.com except AttributeError: 15411569Sgabor.dozsa@arm.com for cpu in self.cpus: 15511569Sgabor.dozsa@arm.com cpu.connectAllPorts(bus) 15611569Sgabor.dozsa@arm.com 15711569Sgabor.dozsa@arm.com 15811569Sgabor.dozsa@arm.comdef addCaches(system, last_cache_level): 15911569Sgabor.dozsa@arm.com cluster_mem_bus = system.membus 16011569Sgabor.dozsa@arm.com assert last_cache_level >= 1 and last_cache_level <= 3 16111569Sgabor.dozsa@arm.com for cluster in system._clusters: 16211569Sgabor.dozsa@arm.com cluster.addL1() 16311569Sgabor.dozsa@arm.com if last_cache_level > 1: 16411569Sgabor.dozsa@arm.com for cluster in system._clusters: 16511569Sgabor.dozsa@arm.com cluster.addL2(cluster.clk_domain) 16611569Sgabor.dozsa@arm.com if last_cache_level > 2: 16711569Sgabor.dozsa@arm.com max_clock_cluster = max(system._clusters, 16811569Sgabor.dozsa@arm.com key=lambda c: c.clk_domain.clock[0]) 16911569Sgabor.dozsa@arm.com system.l3 = devices.L3(clk_domain=max_clock_cluster.clk_domain) 17011569Sgabor.dozsa@arm.com system.toL3Bus = L2XBar(width=64) 17111569Sgabor.dozsa@arm.com system.toL3Bus.master = system.l3.cpu_side 17211569Sgabor.dozsa@arm.com system.l3.mem_side = system.membus.slave 17311569Sgabor.dozsa@arm.com cluster_mem_bus = system.toL3Bus 17411569Sgabor.dozsa@arm.com 17511569Sgabor.dozsa@arm.com return cluster_mem_bus 17611569Sgabor.dozsa@arm.com 17711569Sgabor.dozsa@arm.com 17811569Sgabor.dozsa@arm.comdef main(): 17911569Sgabor.dozsa@arm.com parser = argparse.ArgumentParser( 18011569Sgabor.dozsa@arm.com description="Generic ARM big.LITTLE configuration") 18111569Sgabor.dozsa@arm.com 18211569Sgabor.dozsa@arm.com parser.add_argument("--restore-from", type=str, default=None, 18311569Sgabor.dozsa@arm.com help="Restore from checkpoint") 18411569Sgabor.dozsa@arm.com parser.add_argument("--dtb", type=str, default=default_dtb, 18511569Sgabor.dozsa@arm.com help="DTB file to load") 18611569Sgabor.dozsa@arm.com parser.add_argument("--kernel", type=str, default=default_kernel, 18711569Sgabor.dozsa@arm.com help="Linux kernel") 18811569Sgabor.dozsa@arm.com parser.add_argument("--disk", action="append", type=str, default=[], 18911569Sgabor.dozsa@arm.com help="Disks to instantiate") 19011569Sgabor.dozsa@arm.com parser.add_argument("--bootscript", type=str, default=default_rcs, 19111569Sgabor.dozsa@arm.com help="Linux bootscript") 19211569Sgabor.dozsa@arm.com parser.add_argument("--atomic", action="store_true", default=False, 19311569Sgabor.dozsa@arm.com help="Use atomic CPUs") 19411569Sgabor.dozsa@arm.com parser.add_argument("--kernel-init", type=str, default="/sbin/init", 19511569Sgabor.dozsa@arm.com help="Override init") 19611569Sgabor.dozsa@arm.com parser.add_argument("--big-cpus", type=int, default=1, 19711569Sgabor.dozsa@arm.com help="Number of big CPUs to instantiate") 19811569Sgabor.dozsa@arm.com parser.add_argument("--little-cpus", type=int, default=1, 19911569Sgabor.dozsa@arm.com help="Number of little CPUs to instantiate") 20011569Sgabor.dozsa@arm.com parser.add_argument("--caches", action="store_true", default=False, 20111569Sgabor.dozsa@arm.com help="Instantiate caches") 20211569Sgabor.dozsa@arm.com parser.add_argument("--last-cache-level", type=int, default=2, 20311569Sgabor.dozsa@arm.com help="Last level of caches (e.g. 3 for L3)") 20411569Sgabor.dozsa@arm.com parser.add_argument("--big-cpu-clock", type=str, default="2GHz", 20511569Sgabor.dozsa@arm.com help="Big CPU clock frequency") 20611569Sgabor.dozsa@arm.com parser.add_argument("--little-cpu-clock", type=str, default="1GHz", 20711569Sgabor.dozsa@arm.com help="Little CPU clock frequency") 20811569Sgabor.dozsa@arm.com 20911569Sgabor.dozsa@arm.com m5.ticks.fixGlobalFrequency() 21011569Sgabor.dozsa@arm.com 21111569Sgabor.dozsa@arm.com options = parser.parse_args() 21211569Sgabor.dozsa@arm.com 21311569Sgabor.dozsa@arm.com if options.atomic: 21411569Sgabor.dozsa@arm.com cpu_config = { 'cpu' : AtomicSimpleCPU } 21511569Sgabor.dozsa@arm.com big_cpu_config, little_cpu_config = cpu_config, cpu_config 21611569Sgabor.dozsa@arm.com else: 21711569Sgabor.dozsa@arm.com big_cpu_config = { 'cpu' : CpuConfig.get("arm_detailed"), 21811569Sgabor.dozsa@arm.com 'l1i' : devices.L1I, 21911569Sgabor.dozsa@arm.com 'l1d' : devices.L1D, 22011569Sgabor.dozsa@arm.com 'wcache' : devices.WalkCache, 22111569Sgabor.dozsa@arm.com 'l2' : devices.L2 } 22211569Sgabor.dozsa@arm.com little_cpu_config = { 'cpu' : MinorCPU, 22311569Sgabor.dozsa@arm.com 'l1i' : devices.L1I, 22411569Sgabor.dozsa@arm.com 'l1d' : devices.L1D, 22511569Sgabor.dozsa@arm.com 'wcache' : devices.WalkCache, 22611569Sgabor.dozsa@arm.com 'l2' : devices.L2 } 22711569Sgabor.dozsa@arm.com 22811569Sgabor.dozsa@arm.com big_cpu_class = big_cpu_config['cpu'] 22911569Sgabor.dozsa@arm.com little_cpu_class = little_cpu_config['cpu'] 23011569Sgabor.dozsa@arm.com 23111569Sgabor.dozsa@arm.com kernel_cmd = [ 23211569Sgabor.dozsa@arm.com "earlyprintk=pl011,0x1c090000", 23311569Sgabor.dozsa@arm.com "console=ttyAMA0", 23411569Sgabor.dozsa@arm.com "lpj=19988480", 23511569Sgabor.dozsa@arm.com "norandmaps", 23611569Sgabor.dozsa@arm.com "loglevel=8", 23711569Sgabor.dozsa@arm.com "mem=%s" % default_mem_size, 23811569Sgabor.dozsa@arm.com "root=/dev/vda1", 23911569Sgabor.dozsa@arm.com "rw", 24011569Sgabor.dozsa@arm.com "init=%s" % options.kernel_init, 24111569Sgabor.dozsa@arm.com "vmalloc=768MB", 24211569Sgabor.dozsa@arm.com ] 24311569Sgabor.dozsa@arm.com 24411569Sgabor.dozsa@arm.com root = Root(full_system=True) 24511569Sgabor.dozsa@arm.com 24611569Sgabor.dozsa@arm.com assert big_cpu_class.memory_mode() == little_cpu_class.memory_mode() 24711569Sgabor.dozsa@arm.com disks = default_disk if len(options.disk) == 0 else options.disk 24811569Sgabor.dozsa@arm.com system = createSystem(options.kernel, big_cpu_class.memory_mode(), 24911569Sgabor.dozsa@arm.com options.bootscript, disks=disks) 25011569Sgabor.dozsa@arm.com 25111569Sgabor.dozsa@arm.com root.system = system 25211569Sgabor.dozsa@arm.com system.boot_osflags = " ".join(kernel_cmd) 25311569Sgabor.dozsa@arm.com 25411569Sgabor.dozsa@arm.com # big cluster 25511569Sgabor.dozsa@arm.com if options.big_cpus > 0: 25611569Sgabor.dozsa@arm.com system.bigCluster = CpuCluster() 25711569Sgabor.dozsa@arm.com system.bigCluster.addCPUs(big_cpu_config, options.big_cpus, 25811569Sgabor.dozsa@arm.com options.big_cpu_clock) 25911569Sgabor.dozsa@arm.com 26011569Sgabor.dozsa@arm.com 26111569Sgabor.dozsa@arm.com # LITTLE cluster 26211569Sgabor.dozsa@arm.com if options.little_cpus > 0: 26311569Sgabor.dozsa@arm.com system.littleCluster = CpuCluster() 26411569Sgabor.dozsa@arm.com system.littleCluster.addCPUs(little_cpu_config, options.little_cpus, 26511569Sgabor.dozsa@arm.com options.little_cpu_clock) 26611569Sgabor.dozsa@arm.com 26711569Sgabor.dozsa@arm.com # add caches 26811569Sgabor.dozsa@arm.com if options.caches: 26911569Sgabor.dozsa@arm.com cluster_mem_bus = addCaches(system, options.last_cache_level) 27011569Sgabor.dozsa@arm.com else: 27111569Sgabor.dozsa@arm.com if big_cpu_class.require_caches(): 27211569Sgabor.dozsa@arm.com m5.util.panic("CPU model %s requires caches" % str(big_cpu_class)) 27311569Sgabor.dozsa@arm.com if little_cpu_class.require_caches(): 27411569Sgabor.dozsa@arm.com m5.util.panic("CPU model %s requires caches" % 27511569Sgabor.dozsa@arm.com str(little_cpu_class)) 27611569Sgabor.dozsa@arm.com cluster_mem_bus = system.membus 27711569Sgabor.dozsa@arm.com 27811569Sgabor.dozsa@arm.com # connect each cluster to the memory hierarchy 27911569Sgabor.dozsa@arm.com for cluster in system._clusters: 28011569Sgabor.dozsa@arm.com cluster.connectMemSide(cluster_mem_bus) 28111569Sgabor.dozsa@arm.com 28211569Sgabor.dozsa@arm.com # Linux device tree 28311569Sgabor.dozsa@arm.com system.dtb_filename = SysPaths.binary(options.dtb) 28411569Sgabor.dozsa@arm.com 28511569Sgabor.dozsa@arm.com # Get and load from the chkpt or simpoint checkpoint 28611569Sgabor.dozsa@arm.com if options.restore_from is not None: 28711569Sgabor.dozsa@arm.com m5.instantiate(options.restore_from) 28811569Sgabor.dozsa@arm.com else: 28911569Sgabor.dozsa@arm.com m5.instantiate() 29011569Sgabor.dozsa@arm.com 29111569Sgabor.dozsa@arm.com # start simulation (and drop checkpoints when requested) 29211569Sgabor.dozsa@arm.com while True: 29311569Sgabor.dozsa@arm.com event = m5.simulate() 29411569Sgabor.dozsa@arm.com exit_msg = event.getCause() 29511569Sgabor.dozsa@arm.com if exit_msg == "checkpoint": 29611569Sgabor.dozsa@arm.com print "Dropping checkpoint at tick %d" % m5.curTick() 29711569Sgabor.dozsa@arm.com cpt_dir = os.path.join(m5.options.outdir, "cpt.%d" % m5.curTick()) 29811569Sgabor.dozsa@arm.com m5.checkpoint(os.path.join(cpt_dir)) 29911569Sgabor.dozsa@arm.com print "Checkpoint done." 30011569Sgabor.dozsa@arm.com else: 30111569Sgabor.dozsa@arm.com print exit_msg, " @ ", m5.curTick() 30211569Sgabor.dozsa@arm.com break 30311569Sgabor.dozsa@arm.com 30411569Sgabor.dozsa@arm.com sys.exit(event.getCode()) 30511569Sgabor.dozsa@arm.com 30611569Sgabor.dozsa@arm.com 30711569Sgabor.dozsa@arm.comif __name__ == "__m5_main__": 30811569Sgabor.dozsa@arm.com main() 309